M16C62P_06 Datasheet, PDF (83/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
8. Bus
8.2.10 Software Wait
Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits in the
CSR register, and the CSE register. The SFR area is unaffected by these control bits. This area is always
accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 register. See Table 8.8 Bit
and Bus Cycle Related to Software Wait for details.
To use the RDY signal, set the corresponding CS3W to CS0W bit to “0” (with wait state). Figure 8.6 shows the
CSE Register. Table 8.8 shows the Bit and Bus Cycle Related to Software Wait. Figure 8.7 and 8.8 show the
Typical Bus Timings Using Software Wait.
Chip Select Expansion Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
CSE
001Bh
00h
Bit Symbol
Bit Name
Function
RW
_____
CS0 Wait Expansion Bit ⁽¹⁾
b1 b0
CSE00W
0 0 : 1 w ait
RW
0 1 : 2 w aits
CSE01W
1 0 : 3 w aits
RW
1 1 : Do not set
_____
CS1 Wait Expansion Bit ⁽¹⁾
b3 b2
CSE10W
0 0 : 1 w ait
RW
0 1 : 2 w aits
CSE11W
1 0 : 3 w aits
RW
1 1 : Do not set
_____
CS2 Wait Expansion Bit ⁽¹⁾
b5 b4
CSE20W
0 0 : 1 w ait
RW
0 1 : 2 w aits
CSE21W
1 0 : 3 w aits
RW
1 1 : Do not set
_____
CS3 Wait Expansion Bit ⁽¹⁾
b7 b6
CSE30W
0 0 : 1 w ait
RW
0 1 : 2 w aits
CSE31W
1 0 : 3 w aits
RW
1 1 : Do not set
NOTES :
1. Set the CSiW bit (i = 0 to 3) in the CSR register to “0” (w ith w ait state) before w riting to the CSEi1W to CSEi0W bits.
If the CSiW bit needs to be set to “1” (w ithout w ait state), set the CSEi1W to CSEi0W bits to “00b” before setting it.
Figure 8.6 CSE Register
Rev.2.41 Jan 10, 2006 Page 68 of 390
REJ09B0185-0241