M16C62P_06 Datasheet, PDF (122/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
12. Interrupt
12.2 Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts.
12.2.1 Undefined Instruction Interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
12.2.2 Overflow Interrupt
An overflow interrupt occurs when executing the INTO instruction with the O flag in the FLG register set to “1”
(the operation resulted in an overflow). The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
12.2.3 BRK Interrupt
A BRK interrupt occurs when executing the BRK instruction.
12.2.4 INT Instruction Interrupt
An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63 can be
specified for the INT instruction. Because software interrupt Nos. 4 to 31 are assigned to peripheral function
interrupts, the same interrupt routine as for peripheral function interrupts can be executed by executing the INT
instruction.
In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is cleared to
“0” (ISP selected) before executing an interrupt sequence. The U flag is restored from the stack when returning
from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not change state during
instruction execution, and the SP then selected is used.
Rev.2.41 Jan 10, 2006 Page 107 of 390
REJ09B0185-0241