M16C62P_06 Datasheet, PDF (64/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
6. Voltage Detection Circuit
6.1 Low Voltage Detection Interrupt
If the D40 bit in the D4INT register is set to “1” (low voltage detection interrupt enabled), the low voltage detection
interrupt request is generated when the voltage applied to the VCC1 pin is above or below Vdet4.
The low voltage detection interrupt shares the same interrupt vector with the watchdog timer interrupt and
oscillation stop, re-oscillation detection interrupt.
Set the D41 bit in the D4INT register to “1” (enabled) to use the low voltage detection interrupt to exit stop mode.
The D42 bit in the D4INT register is set to “1” as soon as the voltage applied to the VCC1 pin reaches Vdet4 due to
the voltage rise and voltage drop. When the D42 bit changes “0” to “1”, the low voltage detection interrupt request
is generated. Set the D42 bit to “0” by program. However, when the D41 bit is set to “1” and the microcomputer is
in stop mode, the low voltage detection interrupt request is generated regardless of the D42 bit state if the voltage
applied to the VCC1 pin is detected to be above Vdet4. The microcomputer then exits stop mode.
Table 6.1 shows Low Voltage Detection Interrupt Request Generation Conditions.
The DF1 to DF0 bits in the D4INT register determine the sampling period that detects the voltage applied to the
VCC1 pin reaches Vdet4. Table 6.2 shows the Sampling Periods.
Table 6.1 Low Voltage Detection Interrupt Request Generation Conditions
Operating Mode
Normal Operating
Mode ⁽¹⁾
Wait Mode ⁽²⁾
VC27 Bit
1
Stop Mode ⁽²⁾
D40 Bit
1
D41 Bit
−
−
1
D42 Bit
0 to 1
0 to 1
−
−
CM02 Bit
−
0
1
0
VC13 Bit
0 to 1 ⁽³⁾
1 to 0 ⁽³⁾
0 to 1 ⁽³⁾
1 to 0 ⁽³⁾
0 to 1
0 to 1
− : “0”or “1”
1. The status except the wait mode and stop mode is handled as the normal mode. (Refer to 10. Clock
Generation Circuit)
2. Refer to 6.2 Limitations on Exiting Stop Mode, 6.3 Limitations on Exiting Wait Mode.
3. An interrupt request for voltage reduction is generated a sampling time after the value of the VC13
bit has changed.
See the Figure 6.6 Low Voltage Detection Interrupt Generation Circuit Operation Example for
details.
Table 6.2 Sampling Periods
CPU Clock
(D4INT clock)
(MHz)
16
DF1 to DF0=00
(CPU clock divided by 8)
3.0
Sampling Clock (µs)
DF1 to DF0=01
DF1 to DF0=10
(CPU clock divided by 16) (CPU clock divided by 32)
6.0
12.0
DF1 to DF0=11
(CPU clock divided by 64)
24.0
Rev.2.41 Jan 10, 2006 Page 49 of 390
REJ09B0185-0241