M16C62P_06 Datasheet, PDF (125/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
12. Interrupt
12.4.2 Relocatable Vector Tables
The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table
area. Table 12.2 lists the Relocatable Vector Tables. Setting an even address in the INTB register results in the
interrupt sequence being executed faster than in the case of odd addresses.
Table 12.2 Relocatable Vector Tables
Interrupt Source
Vector Address ⁽¹⁾
Address (L) to Address (H)
BRK Instruction ⁽⁵⁾
+0 to +3 (0000h to 0003h)
−(Reserved)
INT3
+16 to +19 (0010h to 0013h)
Timer B5
+20 to +23 (0014h to 0017h)
Timer B4, UART1 Bus Collision Detect ^{(4, 6)} +24 to +27 (0018h to 001Bh)
Timer B3, UART0 Bus Collision Detect ^{(4, 6)} +28 to +31 (001Ch to 001Fh)
SI/O4, INT5 ⁽²⁾
+32 to +35 (0020h to 0023h)
SI/O3, INT4 ⁽²⁾
+36 to +39 (0024h to 0027h)
UART 2 Bus Collision Detection ⁽⁶⁾
+40 to +43 (0028h to 002Bh)
DMA0
+44 to +47 (002Ch to 002Fh)
DMA1
+48 to +51 (0030h to 0033h)
Key Input Interrupt
+52 to +55 (0034h to 0037h)
A/D
+56 to +59 (0038h to 003Bh)
UART2 Transmit, NACK2 ⁽³⁾
+60 to +63 (003Ch to 003Fh)
UART2 Receive, ACK2 ⁽³⁾
+64 to +67 (0040h to 0043h)
UART0 Transmit, NACK0 ⁽³⁾
+68 to +71 (0044h to 0047h)
UART0 Receive, ACK0 ⁽³⁾
+72 to +75 (0048h to 004Bh)
UART1 Transmit, NACK1 ⁽³⁾
+76 to +79 (004Ch to 004Fh)
UART1 Receive, ACK1 ⁽³⁾
+80 to +83 (0050h to 0053h)
Timer A0
+84 to +87 (0054h to 0057h)
Timer A1
+88 to +91 (0058h to 005Bh)
Timer A2
+92 to +95 (005Ch to 005Fh)
Timer A3
+96 to +99 (0060h to 0063h)
Timer A4
+100 to +103 (0064h to 0067h)
Timer B0
+104 to +107 (0068h to 006Bh)
Timer B1
+108 to +111 (006Ch to 006Fh)
Timer B2
+112 to +115 (0070h to 0073h)
INT0
+116 to +119 (0074h to 0077h)
INT1
+120 to +123 (0078h to 007Bh)
INT2
+124 to +127 (007Ch to 007Fh)
Software Interrupt ⁽⁵⁾
+128 to +131 (0080h to 0083h)
to
+252 to +255 (00FCh to 00FFh)
Software
Interrupt
Number
0
1 to 3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
to
63
Reference
M16C/60, M16C/20
Series software manual
12.6 INT interrupt
15. Timers
15. Timers
17. Serial Interface
12.6 INT interrupt
17. Serial Interface
17. Serial Interface
14. DMAC
12.8 Key Input Interrupt
18. A/D Converter
17. Serial Interface
15. Timers
12.6 INT interrupt
M16C/60, M16C/20
Series software manual
NOTES:
1. Address relative to address in INTB.
2. Use the IFSR6 and IFSR7 bits in the IFSR register to select.
3. During I²C mode, NACK and ACK interrupts comprise the interrupt source.
4. Use the IFSR26 and IFSR27 bits in the IFSR2A register to select.
5. These interrupts cannot be disabled using the I flag.
6. Bus collision detection : During IE mode, this bus collision detection constitutes the factor of an interrupt.
During I²C mode, however, a start condition or a stop condition detection constitutes
the factor of an interrupt.
Rev.2.41 Jan 10, 2006 Page 110 of 390
REJ09B0185-0241