M16C62P_06 Datasheet, PDF (278/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
21. Programmable I/O Ports
Port Pi Register (i=0 to 7 and 9 to 13) ^{(2, 3)}
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
P0 to P3
03E0h, 03E1h, 03E4h, 03E5h
Indeterminate
P4 to P7
03E8h, 03E9h, 03ECh, 03EDh
Indeterminate
P9 to P12
03F1h, 03F4h, 03F5h, 03F8h
Indeterminate
P13
Bit Symbol
03F9h
Bit Name
Indeterminate
Function
RW
Pi_0 Port Pi_0 Bit
Pi_1 Port Pi_1 Bit
Pi_2 Port Pi_2 Bit
Pi_3 Port Pi_3 Bit
Pi_4 Port Pi_4 Bit
The pin level on any I/O port w hich is set for input
RW
mode can be read by reading the corresponding bit in _RW
this register.
The pin level on any I/O port w hich is set for output ^RW
mode can be controlled by w riting to the
RW
orresponding bit in this register
RW
Pi_5 Port Pi_5 Bit
0 : “L” level
RW
Pi_6 Port Pi_6 Bit
1 : “H” level ⁽¹⁾
RW
Pi_7 Port Pi_7 Bit
(i = 0 to 7 and 9 to 13)
RW
NOTES :
1. Since P7_0 and P7_1 are N-channel open drain ports, the data is high-impedance.
2. During memory e_{_}x_{_}t_{_}e_{__}nsio_{_}n_{__}a_{__}nd_{__}m_{_}ic_{_}r_{_}o_{_}p_{__}r_{_}oc_{__}e_{_}ss_{_}o_{__}r_{_}m_{__}o_{_}d_{__}e_{_}s_{_}, the Pi_{_}r_{_}e_{__}g_{_}ist_{_}e_{__}r_{_}f_{_}o_{__}r t_{_}h_{_}e_{___}p_{_}i_{_}ns functioning as bus control pins (A0 to
A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK) cannot be modified.
3. To use ports P11 to P14, set the PU37 bit in the PUR3 register to “1” (enable). If this bit is set to “0” (disable), the P11 to
P14 registers are cleared to “0”.
Port P8 Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
P8
03F0h
Indeterminate
Bit Symbol
Bit Name
Function
RW
P8_0 Port P8_0 Bit
The pin level on any I/O port w hich is set for input mode RW
P8_1
P8_2
P8_3
P8_4
P8_5
P8_6
P8_7
Port P8_1 Bit
Port P8_2 Bit
Port P8_3 Bit
Port P8_4 Bit
Port P8_5 Bit
Port P8_6 Bit
Port P8_7 Bit
can be read by reading the corresponding bit in this
RW
register.
RW
The pin level on any I/O port w hich is set for output
RW
mode can be controlled by w riting to the corresponding _RW
bit in this register (except for P8_5)
RO
0 : “L” level
RW
1 : “H” level
RW
Figure 21.8 Pi Registers
Rev.2.41 Jan 10, 2006 Page 263 of 390
REJ09B0185-0241