M16C62P_06 Datasheet, PDF (176/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
.
15. Timers
Timer Bi Mode Register (i=0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
01
Symbol
Address
After Reset
TB0MR to TB2MR
039Bh to 039Dh
00XX0000b
TB3MR to TB5MR
035Bh to 035Dh
00XX0000b
Bit Symbol
Bit Name
Function
RW
TMOD0 Operation Mode Select Bit
b1 b0
RW
TMOD1
0 1 : Event counter mode
RW
MR0
Count Polarity Select Bit ⁽¹⁾
b3 b2
0 0 : Counts falling edges of external signal
RW
0 1 : Counts rising edges of external signal
1 0 : Counts falling and rising edges
MR1
external signal
RW
1 1 : Do not set to this value
TB0MR, TB3MR registers
Set to “0” in event counter mode
RW
MR2
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When w rite, set to “0”.
—
When read, its content is indeterminate.
When w rite in event counter mode, set to “0”.
MR3 _{When read in event counter mode, its content is indeterminate.}
RO
Has no effect in event counter mode.
TCK0 _{Can be set to “0” or “1”.}
RW
Event Clock Select
0 : Input f rom TBiIN pin ⁽²⁾
TCK1
1 : TBj overflow or underflow
(j = i – 1, how ever, j = 2 if i = 0,
RW
j = 5 if i = 3)
NOTES :
1. Effective w hen the TCK1 bit = 0 (input from TBiIN pin). If the TCK1 bit = 1 (TBj overflow or underflow ), these bits can
be set to “0” or “1”.
2. The port direction bit for the TBiIN pin must be set to “0” (= input mode).
Figure 15.20 TBiMR Register in Event Counter Mode
Rev.2.41 Jan 10, 2006 Page 161 of 390
REJ09B0185-0241