M16C62P_06 Datasheet, PDF (132/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
12. Interrupt
The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP ⁽¹⁾, at the
time of acceptance of an interrupt request, is even or odd. If the stack pointer ⁽¹⁾ is even, the FLG register and
the PC are saved,16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure 12.8 shows the
Operation of Saving Register.
NOTES:
1.When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated by the
U flag. Otherwise, it is the ISP.
(1) SP contains even number
Address
Stack
[SP] − 5 (Odd)
[SP] − 4 (Even)
[SP] − 3(Odd)
[SP] − 2 (Even)
[SP] − 1(Odd)
[SP] (Even)
PCL
PCM
FLGL
FLGH
PCH
Sequence in which order
registers are saved
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
Finished saving registers
in two operations.
(2) SP contains odd number
Address
Stack
Sequence in which order
registers are saved
[SP] − 5 (Even)
[SP] − 4(Odd)
[SP] − 3 (Even)
[SP] − 2(Odd)
[SP] − 1 (Even)
[SP] (Odd)
PCL
PCM
FLGL
FLGH
PCH
(3)
(4)
Saved, 8 bits at a time
(1)
(2)
Finished saving registers
in four operations.
PCH : 4 high-order bits of PC
PCM : 8 middle-order bits of PC
PCL : 8 low-order bits of PC
FLGH : 4 high-order bits of FLG
FLGL : 8 low-order bits of FLG
NOTES :
1. [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 12.8 Operation of Saving Register
Rev.2.41 Jan 10, 2006 Page 117 of 390
REJ09B0185-0241