M16C62P_06 Datasheet, PDF (130/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
12. Interrupt
12.5.5 Interrupt Response Time
Figure 12.6 shows the Interrupt Response Time. The interrupt response or interrupt acknowledge time denotes a
time from when an interrupt request is generated till when the first instruction in the interrupt routine is
executed. Specifically, it consists of a time from when an interrupt request is generated till when the instruction
then executing is completed ((a) on Figure 12.6) and a time during which the interrupt sequence is executed ((b)
on Figure 12.6).
Interrupt request generated Interrupt request acknowledged
Instruction
(a)
Interrupt sequence
(b)
Interrupt response time
Time
Instruction in
interrupt routine
(a) A time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) A time during which the interrupt sequence is executed. For details, see the table
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
Interrupt Vector Address SP Value 16-Bit Bus, Without Wait 8-Bit Bus, Without Wait
Even
Even
18 cycles
20 cycles
Even
Odd
19 cycles
20 cycles
Odd
Even
19 cycles
20 cycles
Odd
Odd
20 cycles
20 cycles
Figure 12.6 Interrupt Response Time
12.5.6 Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the
IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in
Table 12.5 is set in the IPL. Table 12.5 lists the IPL Level That is Set to IPL When a Software or Special
Interrupt is Accepted.
Table 12.5 IPL Level That is Set to IPL When a Software or Special Interrupt is Accepted
Interrupt Sources
Level that is Set to IPL
Watchdog Timer, NMI, Oscillation Stop and Re-Oscillation Detection, ⁷
Low Voltage Detection
Software, Address Match, DBC, Single-Step
Not changed
Rev.2.41 Jan 10, 2006 Page 115 of 390
REJ09B0185-0241