M16C62P_06 Datasheet, PDF (101/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
10. Clock Generation Circuit
Oscillation Stop Detection Register ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol
Address
CM2
000Ch
After Reset
0X000000b ⁽¹¹⁾
Bit Symbol
Bit Name
Function
RW
Oscillation Stop,
0: Oscillation stop, re-oscillation detection
Re-Oscillation Detection
function disabled
CM20
Enable Bit ^{(7, 9, 10,11)}
1: Oscillation stop, re-oscillation detection
RW
function enabled
System Clock Select Bit 2 0: Main clock or PLL clock
CM21
(2, 3, 6, 8, 11, 12)
1: On-chip oscillator clock
RW
(On-chip oscillator oscillates)
Oscillation Stop,
0: Main clock stops, re-oscillation not
CM22 ^{Re-Oscillation Detection}
detected
RW
Flag ⁽⁴⁾
1: Main clock stops, re-oscillation detected
XIN Monitor Flag ⁽⁵⁾
0: Main clock oscillates
CM23
1: Main clock stops
RO
—
Reserved Bit
Set to “0”
(b5-b4)
RW
—
Nothing is assigned. When w rite, set to “0”.
(b6) When read, its content is “0”.
—
Operation Select Bit
0: Oscillation stop detection reset
(w hen an oscillation stop, 1: Oscillation stop, re-oscillation detection
CM27
re-oscillation is detected)⁽¹¹⁾
interrupt
RW
NOTES :
1. Rew rite this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable).
2. When the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is set to “1”
(oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the CM21 bit is set to
“1” (on-chip oscillator clock) if the main clock stop is detected.
3. If the CM20 bit is set to “1” and the CM23 bit is set to “1” (main clock stops), do not set the CM21 bit to “0”.
4. This bit is set to “1” w hen the main clock stop is detected and the main clock re-oscillation is detected. When this
f lag changes state f rom “0” to “1”, an oscillation stop or a re-oscillation detection interrupt is generated. Use this bit in
an interrupt routine to determine the factors of interrupts betw een the oscillation stop and re-oscillation detection
interrupt and the w atchdog timer interrupt. This bit is set to “0” by w riting “0” in a program. (This bit remains
unchanged even if w riting “1”. Nor is it set to “0” w hen an oscillation stop or a re-oscillation detection interrupt
request is acknow ledged.)
When the CM22 bit is set to “1” and an oscillation stop or a re-oscillation is detected, an oscillation stop or a re-
oscillation detection interrupt is not generated.
5. Determine the main clock status by reading the CM23 bit several times in an oscillation stop or a re-oscillation
detection interrupt routine
6. This bit is valid w hen the CM07 bit in the CM0 register is set to “0”.
7. When the PM21 bit in the PM2 register is set to “1” (disable clock modification), this bit remains unchanged even if
w riting to the CM20 bit.
8. Where the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is “1”
(oscillation stop, re-oscillation detection interrupt), and the CM11 bit is set to “1” (PLL clock is selected as the CPU
clock source), the CM21 bit remains unchanged even if a main clock stop is detected. When the CM22 bit is set to
“0” under these conditions, an oscillation stop, a re-oscillation detection interrupt request is generated at main clock
stop detection. Set the CM21 bit to “1” (on-chip oscillator clock) in the interrupt routine.
9. Set the CM20 bit to “0” (disabled) before entering stop mode. Exit stop mode before setting the CM20 bit back to “1”
(enabled).
10. Set the CM20 bit in the CM2 register to “0” (disabled) before setting the CM05 bit in the CM0 register to “1” (main clock
stops).
11. The CM20, CM21 and CM27 bits remain unchanged at the oscillation stop detection reset.
12. When the CM21 bit is set to “0” (on-chip oscillator stops) and the CM05 bit is set to “1” (main clock stops), the CM06
bit is fixed to “1” (divide-by-8 mode) and the CM15 bit is fixed to “1” (drive capacity High).
Figure 10.4 CM2 Register
Rev.2.41 Jan 10, 2006 Page 86 of 390
REJ09B0185-0241