M16C62P_06 Datasheet, PDF (164/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
15. Timers
Timer A2 Mode Register (i=2 to 4)
(when using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
010001
Symbol
Address
After Reset
TA2MR to TA4MR
Bit Symbol
0398h to 039Ah
Bit Name
00h
Function
RW
Operation Mode Select Bit
b1 b0
TMOD0
0 1 : Event counter mode
RW
TMOD1
RW
To use tw o-phase pulse signal processing, set this bit to “0”.
MR0
RW
To use tw o-phase pulse signal processing, set this bit to “0”.
MR1
RW
To use tw o-phase pulse signal processing, set this bit to “1”.
MR2
RW
To use tw o-phase pulse signal processing, set this bit to “0”.
MR3
RW
Count Operation Type Select Bit
0 : Reload type
TCK0
1 : Free-run type
RW
Tw o-phase pulse signal processing 0 : Normal processing operation
TCK1 _{Operation Type Select Bit (1, 2)}
1 : Multiply-by-4 processing operation
RW
NOTES :
1. TCK1 bit is valid for Timer A3 mode register. No matter how this bit is set, Timer A2 and A4 alw ays operate in normal
processing mode and x4 processing mode, respectively.
2. If tw o-phase pulse signal processing is desired, follow ing register settings are required:
• Set the TAiP bit in the UDF register to “1” (tw o-phase pulse signal processing function enabled).
• Set the TAiTGH and TAiTGL bits in the TRGSR register to “00b” (TAiIN pin input).
• Set the port direction bits for TAiIN and TAiOUT to “0” (input mode).
Figure 15.10 TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase pulse
signal processing with Timer A2, A3 and A4)
Rev.2.41 Jan 10, 2006 Page 149 of 390
REJ09B0185-0241