M16C62P_06 Datasheet, PDF (201/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
UART Transmit/Receive Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
UCON
03B0h
X0000000b
Bit Symbol
Bit Name
Function
RW
UART0 Transmit Interrupt Factor 0 : Transmit buffer empty (Tl = 1)
U0IRS _{Select Bit}
1 : Transmission completed (TXEPT = 1)
RW
UART1 Transmit Interrupt Factor 0 : Transmit buffer empty (Tl = 1)
U1IRS _{Select Bit}
1 : Transmission completed (TXEPT = 1)
RW
UART0 Continuous Receive 0 : Continuous receive mode disabled
U0RRM _{Mode Enable Bit}
1 : Continuous receive mode enable
RW
UART1 Continuous Receive 0 : Continuous receive mode disabled
U1RRM _{Mode Enable Bit}
1 : Continuous receive mode enabled
RW
UART1 CLK/CLKS Select Bit 0 Effective w hen CLKMD1 = 1
CLKMD0
0 : Clock output f rom CLK1
RW
1 : Clock output f rom CLKS1
UART1 CLK/CLKS Select Bit 1 ⁽¹⁾ 0 : CLK output is only CLK1
CLKMD1
1 : Transf er clock output f rom multiple pins
RW
function selected
RCSP
Separate UART0
___________
CTS/RTS Bit
_____ _____
0 : CTS/RTS shared pin
_____ _____
1 : CTS/RTS separated
RW
(CTS0 supplied f rom the P6_4 pin)
—
Nothing is assigned. When w rite, set to “0”.
(b7) When read, its content is indeterminate.
—
NOTES :
1. When using multiple transfer clock output pins, make sure the follow ing conditions are met:
CKDIR bit in the U1MR register = 0 (internal clock)
UARTi Special Mode Register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Sy mbol
A ddres s
A f ter Reset
U0SMR to U2SMR
036Fh, 0373h, 0377h
X0000000b
Bit Symbol
Bit Name
Func tion
RW
I²C Mode Select Bit
0 : Other than I²C mode
IICM
1 : I²C mode
RW
A BC
BBS
A rbitration Lost Detecting Flag
Control Bit
Bus Busy Flag
0 : Update per bit
1 : Update per byte
0 : STOP condition detected
1 : STA RT condition detected (busy)
RW
RW⁽¹⁾
—
Reserved Bit
Set to “0”
( b3 ) ^{(4 )}
RW
SCLL sync output enable bit 0 : Disable
LSY N⁽⁴⁾
1 : Enable
Bus Collision Detect Sampling 0 : Rising edge of transf er clock
A BSCS _{Clock Select Bit}
1 : Underf low s ignal of Timer A j ⁽²⁾
RW
A uto Clear Function Select Bit 0 : No auto clear f unction
A CSE _{of Transmit Enable Bit}
1 : A uto clear at occurrence of bus collision
RW
Transmit Start Condition Select 0 : Not synchronized to RXDi
SSS
Bit
1 : Sy nc hroniz ed to RXDi ⁽³⁾
RW
—
Nothing is assigned.
(b7) When w rite, set to “0”. When read, its content is indeterminate.
—
NOTES :
1. The BBS bit is set to “0” by w riting “0” in a program (Writing “1” has no ef f ect).
2. Underf low signal of Timer A 3 in UA RT0, underf low signal of Timer A 4 in UA RT1, underf low signal of Timer A 0 in
UA RT2.
3. When a transf er begins, the SSS bit is set to “0” (Not synchronized to RXDi).
4. The f unction of the bit 3 varies depending on the product.
If the product is M3062LFGPFP or M3062LFGPGP, the bit 3 becomes the LSY N bit.
If the product is other than M3062LFGPFP and M3062LFGPGP, the bit 3 is reserved. Theref ore, set it to 0.
(The LSY N bit is an SCLL sync output enable bit.)
When the LSY N bit is set to “1” and the SCLi pin outputs an "L" level signal, the data bit, such as the P6_2 bit in the P6
register f or SCL0 pin, the P6_6 bit in the P6 register f or SCL1 pin, and the P7_1 bit in the P7 register f or SCL2 pin, is set
to “1”.
Figure 17.10 UCON and UiSMR Registers
Rev.2.41 Jan 10, 2006 Page 186 of 390
REJ09B0185-0241