M16C62P_06 Datasheet, PDF (394/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
24. Precautions
24.15 Flash Memory Version
24.15.1 Functions to Inhibit Rewriting Flash Memory Rewrite
ID codes are stored in addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and
0FFFFBh. If wrong data are written to theses addresses, the flash memory cannot be read or written in standard
serial I/O mode.
The ROMCP register is mapped in address 0FFFFFh. If wrong data is written to this address, the flash memory
cannot be read or written in parallel I/O mode.
In the flash memory version of microcomputer, these addresses are allocated to the vector addresses (H) of
fixed vectors.
24.15.2 Stop mode
When the microcomputer enters stop mode, execute the instruction which sets the CM10 bit to “1” (stop mode)
after setting the FMR01 bit to “0” (CPU rewrite mode disabled) and disabling the DMA transfer.
24.15.3 Wait mode
When shifting to wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing the WAIT
instruction.
24.15.4 Low power dissipation mode, on-chip oscillator low power dissipation
mode
If the CM05 bit is set to “1” (main clock stop), the following commands must not be executed.
• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program
24.15.5 Writing command and data
Write the command code and data at even addresses.
24.15.6 Program Command
Write “xx40h” in the first bus cycle and write data to the write address in the second bus cycle, and an auto
program operation (data program and verify) will start. Make sure the address value specified in the first bus
cycle is the same even address as the write address specified in the second bus cycle.
24.15.7 Lock Bit Program Command
Write “77h” in the first bus cycle and write “xxD0h” to the uppermost address of a block (even address,
however) in the second bus cycle, and the lock bit for the specified block is cleared to “0”. Make sure then
address value specified in the first bus cycle is the same uppermost block address that is specified in the second
bus cycle.
Rev.2.41 Jan 10, 2006 Page 379 of 390
REJ09B0185-0241