M16C62P_06 Datasheet, PDF (235/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
17.1.5 Special Mode 3 (IE mode)
In this mode, one bit of IEBus is approximated with one byte of UART mode waveform.
Table 17.17 lists the Registers to Be Used and Settings in IE Mode. Figure 17.33 shows the Bus Collision
Detect Function-Related BitsBus Collision Detect Function-Related Bits.
If the TXDi pin (i = 0 to 2) output level and RXDi pin input level do not match, a UARTi bus collision detect
interrupt request is generated.
Use the IFSR26 and IFSR27 bits in the IFSR2A register to enable the UART0/UART1 bus collision detect
function.
Table 17.17 Registers to Be Used and Settings in IE Mode
Register
UiTB
UiRB ⁽³⁾
UiBRG
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
IFSR2A
UCON
Bit
Function
0 to 8
Set transmission data
0 to 8
Reception data can be read
OER, FER, PER, SUM Error flag
0 to 7
Set a bit rate
SMD2 to SMD0
Set to “110b”
CKDIR
Select the internal clock or external clock
STPS
Set to “0”
PRY
Invalid because PRYE=0
PRYE
Set to “0”
IOPOL
Select the TXD/RXD input/output polarity
CLK1, CLK0
Select the count source for the UiBRG register
CRS
Invalid because CRD=1
TXEPT
Transmit register empty flag
CRD
Set to “1”
NCH
Select TXDi pin output mode ⁽²⁾
CKPOL
Set to “0”
UFORM
Set to “0”
TE
Set this bit to “1” to enable transmission
TI
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
RI
Reception complete flag
U2IRS ⁽¹⁾
Select the source of UART2 transmit interrupt
U2RRM ^(1),
UiLCH, UiERE
Set to “0”
0 to 3, 7
Set to “0”
ABSCS
Select the sampling timing at which to detect a bus collision
ACSE
Set this bit to “1” to use the auto clear function of transmit enable bit
SSS
Select the transmit start condition
0 to 7
Set to “0”
0 to 7
Set to “0”
0 to 7
Set to “0”
IFSR26, IFSR27
Set to “1”
U0IRS, U1IRS
Select the source of UART0/UART1 transmit interrupt
U0RRM, U1RRM
Set to “0”
CLKMD0
Invalid because CLKMD1 = 0
CLKMD1, RCSP, 7 Set to “0”
NOTES:
1. Set the bit 4 and bit 5 in the U0C0 and U1C1 registers to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are
in the UCON register.
2. TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When write, set to “0”.
3. Not all register bits are described above. Set those bits to “0” when writing to the registers in IE mode.
i= 0 to 2
Rev.2.41 Jan 10, 2006 Page 220 of 390
REJ09B0185-0241