M16C62P_06 Datasheet, PDF (232/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
Table 17.16 Registers to Be Used and Settings in Special Mode 2
Register
UiTB ⁽³⁾
UiRB ⁽³⁾
UiBRG
UiMR ⁽³⁾
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
UCON
Bit
Function
0 to 7
Set transmission data
0 to 7
Reception data can be read
OER
Overrun error flag
0 to 7
Set a bit rate
SMD2 to SMD0 Set to “001b”
CKDIR
Set this bit to “0” for master mode or “1” for slave mode
IOPOL
Set to “0”
CLK1, CLK0
Select the count source for the UiBRG register
CRS
Invalid because CRD = 1
TXEPT
Transmit register empty flag
CRD
Set to “1”
NCH
Select TXDi pin output format ⁽²⁾
CKPOL
Clock phases can be set in combination with the CKPH bit in the UiSMR3 register
UFORM
Set to “0”
TE
Set this bit to “1” to enable transmission
TI
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
RI
Reception complete flag
U2IRS ⁽¹⁾
Select UART2 transmit interrupt factor
U2RRM ⁽¹⁾, UiLCH, Set to “0”
UiERE
0 to 7
Set to “0”
0 to 7
Set to “0”
CKPH
Clock phases can be set in combination with the CKPOL bit in the UiC0 register
NODC
Set to “0”
0, 2, 4 to 7
Set to “0”
0 to 7
Set to “0”
U0IRS, U1IRS
Select UART0 and UART1 transmit interrupt factor
U0RRM, U1RRM Set to “0”
CLKMD0
Invalid because CLKMD1 = 0
CLKMD1, RCSP, 7 Set to “0”
NOTES:
1. Set the bit 4 and bit 5 in the U0C0 and U1C1 register to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are
in the UCON register.
2. TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When write, set to “0”.
3. Not all register bits are described above. Set those bits to “0” when writing to the registers in Special Mode 2.
i = 0 to 2
Rev.2.41 Jan 10, 2006 Page 217 of 390
REJ09B0185-0241