M16C62P_06 Datasheet, PDF (149/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
14. DMAC
14.2 DMA Transfer Cycles
Any combination of even or odd transfer read and write addresses is possible. Table 14.2 lists the DMA Transfer
Cycles. Table 14.3 lists the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles × j + No. of write cycles × k
Table 14.2 DMA Transfer Cycles
Transfer Unit Bus Width
Access
Address
8-bit Transfers 16-bit
(DMBIT= 1) (BYTE= L)
Even
Odd
8-bit
(BYTE = H)
Even
Odd
16-bit Transfers 16-bit
(DMBIT= 0) (BYTE = L)
Even
Odd
8-bit
(BYTE = H)
Even
Odd
— : This condition does not exist.
Single-Chip Mode
No. of Read
Cycles
1
1
—
—
1
2
—
—
No. of Write
Cycles
1
1
—
—
1
2
—
—
Memory Expansion Mode
Microprocessor Mode
No. of Read No. of Write
Cycles
Cycles
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
Table 14.3 Coefficient j, k
Internal Area
Internal ROM,
RAM
SFR
No Wait
With
Wait
1-Wait 2-Wait
(2)
(2)
j
1
2
2
3
k
1
2
2
3
No
Wait
1
2
External Area
Separate Bus
Multiplex Bus
With Wait ⁽¹⁾
1-Wait 2-Wait 3-Wait
2
3
4
2
3
4
With Wait ⁽¹⁾
1-Wait 2-Wait 3-Wait
3
3
4
3
3
4
NOTES:
1. Depends on the set value of CSE register.
2. Depends on the set value of PM20 bit in the PM2 register.
Rev.2.41 Jan 10, 2006 Page 134 of 390
REJ09B0185-0241