M16C62P_06 Datasheet, PDF (291/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
22. Flash Memory Version
22.3.1 EW0 Mode
The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU
rewrite mode enabled) and is ready to accept commands. EW0 mode is selected by setting the FMR11 bit in the
FMR1 register to “0”. To set the FMR01 bit to “1”, set to “1” after first writing “0”.
The software commands control programming and erasing. The FMR0 register or the status register indicates
whether a program or erase operation is completed as expected or not.
22.3.2 EW1 Mode
EW1 mode is selected by setting the FMR11 bit to “1” after the FMR01 bit is set to “1”. (Both bits must be set
to “0” first before setting to “1”.)
The FMR0 register indicates whether or not a program or erase operation has been completed as expected. The
status register cannot be read in EW1 mode.
When an erase/program operation is initiated the CPU halts all program execution until the operation is
completed or erase-suspend is requested.
22.3.3 Flash memory Control Register (FIDR, FMR0 and FMR1 registers)
Figure 22.4 to Figure 22.6 show the FIDR, FMR0 and FMR1 Registers.
Flash Identification Register ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
FIDR
01B4h
Bit Symbol
Bit Name
Flash Module Type
FIDR0 _{Identification Value}
FIDR1
After Reset
XXXXXX00b
Function
RW
b1 b0
0 0 : M16C/62N, M3062GF8N type flash module
RO
1 0 : M16C/62P type flash module
1 1 : M16C/62M, M16C/62A type flash
RO
—
Nothing is assigned. When w rite, set to “0”.
(b7-b2) When read, their contents are indeterminate.
—
NOTES :
1. This register identifies on-chip flash module type of M16C/62 Group. Note, how ever, no chip version is know n by
this register. Follow the procedure described below for the identification.
(a) Write “FFh” to FIDR register,
(b) Read FIDR register, and
(c) Check tw o low -order bits of read value.
Make sure no access to external memories or other SFRs or no interrupts or DMA transfers w ill occur betw een the
above tw o instructions (a) and (b).
Figure 22.4 FIDR Register
Rev.2.41 Jan 10, 2006 Page 276 of 390
REJ09B0185-0241