M16C62P_06 Datasheet, PDF (133/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
12. Interrupt
12.5.8 Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are
restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Thereafter the CPU returns to the program which was being executed before accepting the interrupt request.
Return the other registers saved by a program within the interrupt routine using the POPM or similar instruction
before executing the REIT instruction.
Register bank is switched back to the bank used prior to the interrupt sequence by the REIT instruction.
12.5.9 Interrupt Priority
If two or more interrupt requests are sampled at the same sampling points (a timing to detect whether an
interrupt request is generated or not), the interrupt with the highest priority is acknowledged.
For maskable interrupts (peripheral functions interrupt), any desired priority level can be selected using the
ILVL2 to ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt
priority is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 12.9 shows the
Hardware Interrupt Priority.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Reset
NMI
DBC
High
Watchdog Timer
Oscillation Stop and Re-Oscillation
Detection,
Low Voltage Detection
Peripheral Function
Single Step
Address Match
Low
Figure 12.9 Hardware Interrupt Priority
Rev.2.41 Jan 10, 2006 Page 118 of 390
REJ09B0185-0241