M16C62P_06 Datasheet, PDF (106/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
10. Clock Generation Circuit
10.1.3 On-chip Oscillator Clock
This clock, approximately 1MHz, is supplied by a on-chip oscillator. This clock is used as the clock source for
the CPU and peripheral function clocks. In addition, if the PM22 bit in the PM2 register is “1” (on-chip
oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog
timer (Refer to 13.1 Count source protective mode).
After reset, the on-chip oscillator is turned off. It is turned on by setting the CM21 bit in the CM2 register to
“1” (on-chip oscillator clock), and is used as the clock source for the CPU and peripheral function clocks, in
place of the main clock. If the main clock stops oscillating when the CM20 bit in the CM2 register is “1”
(oscillation stop, re-oscillation detection function enabled) and the CM27 bit is “1” (oscillation stop, re-
oscillation detection interrupt), the on-chip oscillator automatically starts operating, supplying the necessary
clock for the microcomputer.
10.1.4 PLL Clock
The PLL clock is generated PLL frequency synthesizer. This clock is used as the clock source for the CPU and
peripheral function clocks. After reset, the PLL clock is turned off. The PLL frequency synthesizer is activated
by setting the PLC07 bit to “1” (PLL operation). When the PLL clock is used as the clock source for the CPU
clock, wait tsu(PLL) for the PLL clock to be stable, and then set the CM11 bit in the CM1 register to “1”.
Before entering wait mode or stop mode, be sure to set the CM11 bit to “0” (CPU clock source is the main
clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to “0” (PLL
stops). Figure 10.9 shows the Procedure to Use PLL Clock as CPU Clock Source.
The PLL clock frequency is determined by the equation below. When the PLL clock frequency is 16 MHz or
more, set the PM20 bit in the PM2 register to “0” (2 waits).
PLL clock frequency=f(XIN) X (multiplying factor set by the PLC02 to PLC00 bits in the PLC0 register
(However, 10 MHz PLL clock frequency 24 MHz)
The PLC02 to PLC00 bits can be set only once after reset. Table 10.2 shows the Example for Setting PLL
Clock Frequencies.
Table 10.2 Example for Setting PLL Clock Frequencies
XIN (MHz) PLC02
PLC01
PLC00
Multiplying Factor
10
0
0
1
2
5
0
1
0
4
3.33
0
1
1
6
2.5
1
0
0
8
12
0
0
1
2
6
0
1
0
4
4
0
1
1
6
3
1
0
0
8
NOTES:
1. 10MHz ≤ PLL clock frequency ≤ 24MHz.
PLL Clock (MHz) ⁽¹⁾
20
24
Rev.2.41 Jan 10, 2006 Page 91 of 390
REJ09B0185-0241