M16C62P_06 Datasheet, PDF (72/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
7. Processor Mode
Processor Mode Register 1 ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
PM1
0005h
Bit Symbol
Bit Name
PM10
CS2 Area Sw itch Bit
(Data Block Enable Bit) ⁽²⁾
After Reset
0X001000b
Function
RW
0 : 08000h to 26FFFh (Block A disable)
1 : 10000h to 26FFFh (Block A enable)
RW
Port P3_7 to P3_4 Function Select 0 : Address output
PM11
Bit ⁽³⁾
1 : Port function
RW
Watchdog Timer Function Select Bit 0 : Watchdog timer interrupt
PM12
1 : Watchdog timer reset ⁽⁴⁾
RW
Internal Reserved Area Expansion (NOTE 7)
PM13
Bit ⁽⁶⁾
RW
Memory Area Expansion Bit ⁽³⁾
b5 b4
PM14
0 0 : 1-Mbyte mode (Do not expand)
RW
0 1 : Do not set
PM15
1 0 : Do not set
1 1 : 4-Mbyte mode
RW
—
Reserved Bit
Set to “0”.
(b6)
RW
PM17
Wait Bit ⁽⁵⁾
0 : No w ait state
1 : With w ait state (1 w ait)
RW
NOTES :
1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (w rite enable).
2. Set the PM10 bit to “0” for Mask ROM version. For flash memory version, the PM10 bit controls w hether Block A is
enabled or disabled. When the PM10 bit is set to “1”, 0F000h to 0FFFFh can be used as internal ROM area.
In addition, the PM10 bit is automatically set to “1” w hile the FMR01 bit in the FMR0 register is set to “1” (CPU
rew rite mode).
3. Effective w hen the PM01 to PM00 bits are set to “01b” (memory expansion mode) or “11b” (microprocessor
mode).
4. PM12 bit is set to “1” by w riting a “1” in a program (w riting a “0” has no effect).
5. When PM17 bit is set to “1” (w ith w ait state), one w ait state is inserted w hen accessing the internal RAM, or
internal ROM.
When PM17 bit is set to “1” and accesses an external area, set the CSiW bit in the CSR register (i=0 to 3) to “0”
(w ith w ait state).
6. The PM13 bit is automatically set to “1” w hen the FMR01 bit in the FMR0 register is “1” (CPU rew rite mode).
7. The access area is changed by the PM13 bit as listed in the table below .
Access Area
PM13=0
PM13=1
RAM Up to Addresses 00400h to 03FFFh (15 Kbytes) The entire area is usable
Internal
ROM Up to Addresses D0000h to FFFFFh (192 Kbytes) The entire area is usable
Address 04000h to 07FFFh are usable
External _{Address 80000h to CFFFFh are usable}
Address 04000h to 07FFFh are reserved
Address 80000h to CFFFFh are reserved
(Memory expansion mode)
Figure 7.2 PM1 Register
Rev.2.41 Jan 10, 2006 Page 57 of 390
REJ09B0185-0241