M16C62P_06 Datasheet, PDF (245/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
Table 17.20 SI/O3 and SI/O4 Specifications
Item
Specification
Transfer Data Format • Transfer data length: 8 bits
Transfer Clock
• SMi6 bit in SiC (i=3, 4) register = 1 (internal clock) : fj/ (2(n+1))
fj = f1SIO, f8SIO, f32SIO. n = Setting value of SiBRG register 00h to FFh.
• SMi6 bit = 0 (external clock) : Input from CLKi pin ⁽¹⁾
Transmission/Reception • Before transmission/reception can start, meet the following requirements
Start Condition
Write transmit data to the SiTRR register ^{(2, 3)}
Interrupt Request
• When SMi4 bit in SiC register = 0
Generation Timing
The rising edge of the last transfer clock pulse ⁽⁴⁾
When SMi4 = 1
The falling edge of the last transfer clock pulse ⁽⁴⁾
CLKi Pin Function
I/O port, transfer clock input, transfer clock output
SOUTi Pin Function I/O port, transmit data output, high-impedance
SINi Pin Function
I/O port, receive data input
Select Function
• LSB first or MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with
bit 7 can be selected
• Function for setting an SOUTi initial value set function
When the SMi6 bit in the SiC register = 0 (external clock), the SOUTi pin output
level while not transmitting can be selected.
• CLK polarity selection
Whether transmit data is output/input timing at the rising edge or falling edge
of transfer clock can be selected.
NOTES:
1. To set SMi6 bit to “0” (external clock), follow the procedure described below.
• If the SMi4 bit = 0, write transmit data to the SiTRR register while input on the CLKi pin is high. The
same applies when rewriting the SMi7 bit in the SiC register.
• If the SMi4 bit = 1, write transmit data to the SiTRR register while input on the CLKi pin is low. The
same applies when rewriting the SMi7 bit.
• Because shift operation continues as long as the transfer clock is supplied to the SI/Oi circuit, stop
the transfer clock after supplying eight pulses. If the SMi6 bit = 1 (internal clock), the transfer clock
automatically stops.
2. Unlike UART0 to UART2, SI/Oi (i = 3 to 4) is not separated between the transfer register and buffer.
Therefore, do not write the next transmit data to the SiTRR register during transmission.
3. When SMi6 bit = 1 (internal clock), SOUTi retains the last data for a 1/2 transfer clock period after
completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit data is
written to the SiTRR register during this period, SOUTi immediately goes to a high-impedance state,
with the data hold time thereby reduced.
4. When the SMi6 bit = 1 (internal clock), the transfer clock stops in the high state if the SMi4 bit = 0, or
stops in the low state if the SMi4 bit = 1.
Rev.2.41 Jan 10, 2006 Page 230 of 390
REJ09B0185-0241