M16C62P_06 Datasheet, PDF (212/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
17. Serial Interface
17.1.2 Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer data
format. Table 17.5 lists the UART Mode Specifications.
Table 17.5 UART Mode Specifications
Item
Transfer Data Format
Transfer Clock
Transmission, Reception
Control
Transmission Start
Condition
Reception Start Condition
Interrupt Request
Generation Timing
Error Detection
Select Function
Specification
• Character bit (transfer data): Selectable from 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bit: Selectable from 1 or 2 bits
• CKDIR bit in the UiMR(i=0 to 2) register = 0 (internal clock) : fj/ (16(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh
• CKDIR bit = 1 (external clock) : fEXT/(16(n+1))
• fEXT: Input from CLKi pin n :Setting value of UiBRG register 00h to FFh
Selectable from CTS function, RTS function or CTS/RTS function disable
Before transmission can start, meet the following requirements
• The TE bit in the UiC1 register= 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
• If CTS function is selected, input on the CTSi pin = L
Before reception can start, meet the following requirements
• The RE bit in the UiC1 register = 1 (reception enabled)
• Start bit detection
For transmission, one of the following conditions can be selected
• The UiIRS bit ⁽²⁾ = 0 (transmit buffer empty): when transferring data from the UiTB
register to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial interface finished sending data
from the UARTi transmit register
For reception
• When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
• Overrun error ⁽¹⁾
This error occurs if the serial interface started receiving the next data before reading
the UiRB register and received the bit one before the last stop bit of the next data
• Framing error ⁽³⁾
This error occurs when the number of stop bits set is not detected
• Parity error ⁽³⁾
This error occurs when if parity is enabled, the number of “1” in parity and character
bits does not match the number of “1” set
• Error sum flag
This flag is set to “1” when any of the overrun, framing or parity errors occur
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can
be selected
• Serial data logic switch
This function reverses the logic of the transmit/receive data. The start and stop bits
are not reversed.
• TXD, RXD I/O polarity switch
This function reverses the polarities of the TXD pin output and RXD pin input. The
logic levels of all I/O data is reversed.
• Separate CTS/RTS pins (UART0)
CTS0 and RTS0 are input/output from separate pins
NOTES:
1. If an overrun error occurs, the receive data of UiRB register will be indeterminate. The IR bit in the SiRIC
register does not change.
2. The U0IRS and U1IRS bits are bits 0 and 1 in the UCON register. The U2IRS bit is bit 4 in the U2C1 register.
3. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred
from the UARTi receive register to the UiRB register.
Rev.2.41 Jan 10, 2006 Page 197 of 390
REJ09B0185-0241