M16C62P_06 Datasheet, PDF (131/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
12. Interrupt
12.5.7 Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG register,
16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved.
Figure 12.7 shows the Stack Status Before and After Acceptance of Interrupt Request.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use the
PUSHM instruction, and all registers except SP can be saved with a single instruction.
Address
MSB
Stack
LSB
Address
Stack
MSB
LSB
m−4
m−3
m−2
m−1
m
Content of previous stack
m + 1 ^{Content of previous stack}
[SP]
SP value before
interrupt request is
accepted.
m−4
PCL
m−3
m−2
PCM
FLGL
m − 1 FLGH
PCH
m
Content of previous stack
m + 1 Content of previous stack
[SP]
New SP value
Stack status before interrupt request
is acknowledged
Stack status after interrupt request
is acknowledged
PCH : 4 high-order bits of PC
PCM : 8 middle-order bits of PC
PCL : 8 low-order bits of PC
FLGH : 4 high-order bits of FLG
FLGL : 8 low-order bits of FLG
Figure 12.7 Stack Status Before and After Acceptance of Interrupt Request
Rev.2.41 Jan 10, 2006 Page 116 of 390
REJ09B0185-0241