M16C62P_06 Datasheet, PDF (386/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
24. Precautions
24.9.1.3 Timer A (One-shot Timer Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4)
register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before
setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the TA0TGL and TA0TGH bits and the TRGSR register are modified
while the TAiS bit remains “0” (count stops) regardless whether after reset or not.
When setting TAiS bit to “0” (count stop), the followings occur:
• A counter stops counting and a content of reload register is reloaded.
• TAiOUT pin outputs “L”.
• After one cycle of the CPU clock, the IR bit in the TAiIC register is set to “1” (interrupt request).
Output in one-shot timer mode synchronizes with a count source internally generated. When an external trigger
has been selected, one-cycle delay of a count source as maximum occurs between a trigger input to TAiIN pin
and output in one-shot timer mode.
The IR bit is set to “1” when timer operating mode is set with any of the following procedures:
• Select one-shot timer mode after reset.
• Change an operating mode from timer mode to one-shot timer mode.
• Change an operating mode from event counter mode to one-shot timer mode.
To use the Timer Ai interrupt (the IR bit), set the IR bit to “0” after the changes listed above have been made.
When a trigger occurs, while counting, a counter reloads the reload register to continue counting after
generating a re-trigger and counting down once. To generate a trigger while counting, generate a second trigger
between occurring the previous trigger and operating longer than one cycle of a timer count source.
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase
output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a high-
impedance state.
24.9.1.4 Timer A (Pulse Width Modulation Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4)
register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before
setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, TA0TGL and TA0TGH bits and the TRGSR register are modified while
the TAiS bit remains “0” (count stops) regardless whether after reset or not.
The IR bit is set to “1” when setting a timer operating mode with any of the following procedures:
• Select the PWM mode after reset.
• Change an operating mode from timer mode to PWM mode.
• Change an operating mode from event counter mode to PWM mode.
To use the Timer Ai interrupt (interrupt request bit), set the IR bit to “0” by program after the above listed
changes have been made.
When setting TAiS register to “0” (count stop) during PWM pulse output, the following action occurs:
• Stop counting.
• When TAiOUT pin is output “H”, output level is set to “L” and the IR bit is set to “1”.
• When TAiOUT pin is output “L”, both output level and the IR bit remains unchanged.
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase
output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a high-
impedance state.
Rev.2.41 Jan 10, 2006 Page 371 of 390
REJ09B0185-0241