M16C62P_06 Datasheet, PDF (102/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
10. Clock Generation Circuit
Peripheral Clock Select Register ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
000000
Symbol
Address
After Reset
PCLKR
025Eh
00000011b
Bit Symbol
Bit Name
Function
RW
Timers A, B Clock Select Bit
0 : f2
PCLK0 _{(Clock source for Timers A , B, and the dead timer) 1 : f1}
RW
SI/O Clock Select Bit
0 : f2SIO
PCLK1 ^{(Clock source for UART0 to UART2, SI/O3, and}
1 : f1SIO
RW
SI/O4)
—
Reserved bit
(b7-b2)
Set to “0”
RW
NOTES :
1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable).
Processor Mode Register 2 ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol
Address
After Reset
PM2
001Eh
XXX00000b
Bit Symbol
Bit Name
Function
RW
Specifying Wait w hen Accessing 0 : 2 w aits
PM20 _{SFR at PLL Operation (2)}
1 : 1 w aits
RW
System Clock Protective Bit ^{(3, 4)} 0 : Clock is protected by PRCR register
PM21
1 : Clock modification disabled
RW
PM22
WDT Count Source
Protective Bit ^{(3, 5)}
0 : CPU clock is used for the w atchdog timer
count source
1 : On-chip oscillator clock is used for the
RW
w atchdog timer count source
—
Reserved Bit
Set to “0”
(b4-b3)
RW
—
Nothing is assigned. When w rite, set to “0”.
(b7-b5) When read, their contents are indeterminate.
—
NOTES :
1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (w rite enable).
2. The PM20 bit become effective w hen PLC07 bit in the PLC0 register is set to “1” (PLL on). Change the PM20 bit
w hen the PLC07 bit is set to “0” (PLL off). Set the PM20 bit to “0” (2 w aits) w hen PLL clock > 16MHz.
3. Once this bit is set to “1”, it cannot be cleared to “0” in a program.
4. If the PM21 bit is set to “1”, w riting to the follow ing bits has no effect:
CM02 bit in CM0 register
CM05 bit in CM0 register (main clock does not stop)
CM07 bit in CM0 register (clock source for the CPU clock does not change)
CM10 bit in CM1 register (stop mode is not entered)
CM11 bit in CM1 register (clock source for the CPU clock does not change)
CM20 bit in CM2 register (oscillation stop, re-oscillation detection function settings do not change)
All bits in PLC0 register (PLL frequency synthesizer settings do not change)
Be aw are that the WAIT instruction cannot be executed w hen the PM21 bit = 1.
5. Setting the PM22 bit to “1” results in the follow ing conditions:
• The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the w atchdog timer count source.
• The CM10 bit is disabled against w rite. (Writing a “1” has no effect, nor is stop mode entered.)
• The w atchdog timer does not stop w hen in w ait mode or hold state.
Figure 10.5 PCLKR Register and PM2 Register
Rev.2.41 Jan 10, 2006 Page 87 of 390
REJ09B0185-0241