M16C62P_06 Datasheet, PDF (248/421 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

M16C/62P Group (M16C/62P, M16C/62PT)
18. A/D Converter
18. A/D Converter
The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method configured
with a capacitive-coupling amplifier. The analog inputs share the pins with P10_0 to P10_7, P9_5, P9_6, and P0_0 to
P0_7, and P2_0 to P2_7. Similarly, ADTRG input shares the pin with P9_7. Therefore, when using these inputs, make
sure the corresponding port direction bits are set to “0” (= input mode).
When not using the A/D converter, set the VCUT bit to “0” (= Vref unconnected), so that no current will flow from the
VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
The A/D conversion result is stored in the ADi register bits for ANi, AN0_i, and AN2_i pins (i = 0 to 7).
Table 18.1 shows the Performance of A/D Converter. Figure 18.1 shows the A/D Converter Block Diagram, and
Figures 18.2 and 18.3 show the A/D converter-related registers.
Table 18.1 Performance of A/D Converter
Item
Method of A/D Conversion
Analog input Voltage ⁽¹⁾
Operating clock φAD ⁽²⁾
Resolution
Integral Nonlinearity Error
Operating Modes
Analog Input Pins ⁽³⁾
A/D Conversion Start
Condition
Conversion Speed
Performance
Successive approximation (capacitive coupling amplifier)
0V to AVCC (VCC1)
fAD/divide-by-2 of fAD/divide-by-3 of fAD/divide-by-4 of fAD/divide-by-6 of
fAD/divide-by-12 of fAD
8-bit or 10-bit (selectable)
When AVCC = VREF = 5V
• With 8-bit resolution: ±2LSB
• With 10-bit resolution
AN0 to AN7 input, AN0_0 to AN0_7 input and AN2_0 to AN2_7 input : 3LSB
ANEX0 and ANEX1 input (including mode in which external Op-Amp is connected)
: ±7LSB
When AVCC = VREF = 3.3V
• With 8-bit resolution: ±2LSB
• With 10-bit resolution
AN0 to AN7 input, AN0_0 to AN0_7 input and AN2_0 to AN2_7 input : ±5LSB
ANEX0 and ANEX1 input (including mode in which external Op-Amp is connected)
: ±7LSB
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1) + 8 pins (AN0_0 to AN0_7)
+ 8 pins (AN2_0 to AN2_7)
• Software trigger
The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
• External trigger (retriggerable)
Input on the ADTRG pin changes state from high to low after the ADST bit is set to “1”
(A/D conversion starts)
• Without sample and hold function
8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles
• With sample and hold function
8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles
NOTES:
1. Does not depend on use of sample and hold function.
2. φAD frequency must be 12 MHz or less. And divide the fAD if VCC1 is less than 4.0V, and φAD frequency into
10 MHz or less.
When sample & hold is disabled, φAD frequency must be 250kHz or more.
When sample & hold is enabled, φAD frequency must be 1MHz or more.
3. If VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins.
Rev.2.41 Jan 10, 2006 Page 233 of 390
REJ09B0185-0241