MB87P2020 Datasheet, PDF (95/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

SDRAM Controller
Table 3-1: Configuration Information of SDC
Symbol
Bits
Description
Reset Value
SDCFLAG_BUSY [0]
CBPbusy: Set these flag before changing the 0
power on initialization period or the sequencer
RAM. Reset it after the access make changes
take affect.
SDCFLAG_DQMEN [1]
DQM partial write feature^e: Optimize byte/
8bpp and half word/16bpp access if set to 1.
0
Jasmine only
PHA[0:15]
[22:12]
[19:10]
Layer Start Addresses: Row address offset for
start position of each layer. First bit positions
for Lavender, second for Jasmine. [22/19:0]
can be handled as byte address, but only shown
bits are stored.
undefined
DSZ_X[0:15]
[29:16] Layer Widths: X component of Layer Size in undefined
pixel
CSPC_CSC[0:15]
[3:0] Color Depth Table: Color definition code for undefined
evaluation of the number of bits per pixel (bpp)
a.Lavender only. Jasmine works with single bank.
b.Has no effect for Jasmine.
c.Fixed and not accessible for Jasmine.
d.DCBT interface timing adjustable for Lavender only.
e.Jasmine only.
3.2 Core clock dependent Timing Configuration
3.2.1 General Setup
SDRAM access wait states and refresh periods are configurable to support a wide range of scalability in
matter of system performance and power consumption. Additional to the row refresh time out value the re-
fresh sequence in the micro program sequencer is adaptable for its dedicated core frequency.
The configuration tool generates optimized settings for a given core clock frequency to met best perform-
ance result. If a fixed setting should be used over a certain frequency range (i.e. if clock scaling is used with-
out the effort spending for re-configuration) the minimum frequency is required to calculate the refresh
period and the highest frequency should be used to calculate the values for the wait state timers. Thus refresh
condition and minimum access timing is always satisfied.
3.2.2 Refresh Configuration for integrated DRAM (Jasmine)
Setup of minimum refresh rate is based on core clock cycles. Thus the value for the refresh period has to be
configured for its dedicated core clock frequency. Additional to the core frequency, maximum junction tem-
perature has significant influence on refresh period.
• Tjmax = up to 100 degC : tREF = 16.4ms
• Tjmax = 101 to 110 degC : tREF = 8.2ms
• Tjmax = 111 to 125 degC : tREF = 4.1ms
Assumed Row Refresh duration for all 1024 rows is evenly distributed to refresh all rows within above spec-
ification, refresh timing of 16/8/4 us have to be set up. For automotive temperature range 4 us are required.
Configuration
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