MB87P2020 Datasheet, PDF (50/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
• WNDOF0_OFF, WNDOF1_OFF to define an offset in MCU address space
• WNDSZ0_SIZE, WNDSZ1_SIZE to define SDRAM window size for MCU and SDRAM address space
• WNDSD0_OFF, WNDSD1_OFF to define SDRAM offset
All these parameters are explained in detail in table 2-1.
As displayed in figure 1-3 2 MByte (2²¹ Byte) - 256 kByte (register space) = 1.75 MByte can be used for
both windows within MCU address space. This address space is equal in Lavender and Jasmine while the
available SDRAM memory differs according to table 1-6. For Jasmine it is possible to map the entire
SDRAM memory into ULB’s SDRAM space in order to have linear access to SDRAM. For Lavender only
parts of SDRAM can be mapped to MCU address space at one given time but a dynamic reconfiguration is
possible.
Table 1-6: SDRAM memory for Lavender and Jasmine
Display Controller
Lavender
Jasmine
SDRAM type
external
internal
SDRAM size
8 MByte (64 MBit)
1 MByte (8 MBit)
All to one chip select signal connected display controllers share the available SDRAM space (1.75 MByte).
There is no additional restriction about the size or order of SDRAM windows of different controllers.
Figure 1-4 gives just one example but many more configurations are possible.
Gaps between SDRAM windows for a particular display controller are handled by ULB as well as SDRAM
windows of other controllers. Both possibilities can not be distinguished by the address decoder and they
produce an empty space hit which means that no data are driven for read access and a write access is simply
ignored.
Within one display controller overlapping SDRAM windows are allowed; this is controlled by address de-
coder priority according to table 1-5. This is not true for SDRAM windows from different controllers. Write
access is possible; the value is written to all SDRAM windows mapped to this address. Read access is not
possible and can damage display controller or MCU because no ULB bus driving control is available be-
tween different display controllers.
Note: There is no control for overlapping windows of more than one display controller
within SDRAM space. Reading from such an area can damage display controller
or MCU.
With help of SDRAM windows the SDRAM memory can be written or read with physical SDRAM ad-
dresses via a display controller component called ’DPA’ (Direct Physical Memory Access). In difference
to this addressing mode all drawing functions use a logical address (pixel coordinates with (layer, x, y)).
The SDRAM controller (SDC) within the display controller maps the logical pixel coordinates to a physical
SDRAM address. This mapping is block based¹ and differs between Lavender and Jasmine since it depends
on SDRAM architecture. A picture previously generated by Pixel Processor (PP) with help of drawing/bit-
map commands can not be read back in a linear manner because the logical to physical address mapping
has to be performed in order to get the right physical address for a given logical address (layer, x, y). Also
for writing graphics which should be displayed by the Graphic Processing Unit (GPU) of a display control-
ler the logical to physical mapping has to be taken into account. The easiest and most portable way (between
Lavender and Jasmine) to write or read to/from logical address space is to use PP commands. In this case
the mapping is done automatically and controller independent in hardware.
The physical SDRAM windows can be used for any kind of data as long they do not present a picture which
should be displayed by GPU. Within one SDRAM window a linear access to the data is possible.
Because the start address of each layer can be set in physical SDRAM addresses it is possible to divide the
SDRAM memory between layer and user data. Note that there is no layer overrun control implemented in
hardware within the display controller.
While the SDRAM memory windows are mapped into the MCU address space the access is basically or-
ganised as normal register access. But there are some important differences compared to normal register
1. See SDC specification for details.
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