MB87P2020 Datasheet, PDF (31/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

Clock Unit
ClkPdR (Clock Power Down Register) is a set of enable bits for the clocks provided to the dedicated GDC
modules. A bit set to ’1’ means the clock is enabled. If a module requires multiple clocks (inverted ones or
different domains) the enable bit switches all these lines.
Additional ClkPdR controls the work of the PLL and gives status information about it’s lock-state. Also a
global GDC reset function can be executed by setting a configuration bit of this register.
Table 1-1: CU registers
Register Bit
Function
ClkConR [31:30] Direct Clock Source
Description
00 Crystal oszillator (reset default)
01 Pixel clock
10 MCU Bus clock
11 reserved clock input (RCLK^a)
Reset
Value
"00"
[29:24] System clock prescaler [5:0] system clock prescaler value
0
(DIV z)
[23:22] PLL Clock Source
00 Crystal oszillator (reset default)
"00"
01 Pixel clock
10 MCU Bus clock
11 reserved clock input (RCLK)
[21:16] PLL Feedback divider [5:0] pll multiplier value
0
(DIV y)
[15] System Clock Select
0 Direct
’0’
1 PLL output
[14] Pixel Clock Select
0 Direct
’0’
1 PLL output
[13] Inverted Pixel Clock
0 not inverted
’0’
1 inverted
[12] Output disable
DIS_PIXCLK
0 internal pixelclock (output)
’1’
1 external pixelclock (input), high-Z
output
[11]
reserved test operation^{b 0 normal operation}
’0’
1 core clock output on pin SPB_TST
[10:0] Pixel clock prescaler
[10:0] pixelclock prescaler value
0
(DIV x)
Functional Description
Page 31