MB87P2020 Datasheet, PDF (32/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
Register Bit
ClkPdR 0
1
2
3
4
5
6
7
8
9
10
11
12
Table 1-1: CU registers
Function
Description
PP/PE Pixel engine clock 0 = disable, 1 = enable
enable
PP/MAU clock enable 0 = disable, 1 = enable
PP/MCP clock enable 0 = disable, 1 = enable
AAF clock enable
0 = disable, 1 = enable
DIPA clock enable
0 = disable, 1 = enable
VIS clock enable
0 = disable, 1 = enable
SDC clock enable
0 = disable, 1 = enable
CCFL clock enable
0 = disable, 1 = enable
SPB clock enable
0 = disable, 1 = enable
ULB clock enable
0 = disable, 1 = enable
GPU clock enable
0 = disable, 1 = enable
PLL enable
0 = power down , 1 = run mode
VIC clock invert
(Jasmine)
0 = not inverted, 1 = inverted
PLL Lock (Lavender)
0 = unlocked, 1 = locked (read only)^c
Reset
Value
’0’
’0’
’0’
’0’
’0’
’0’
’0’
’0’
’0’
’0’
’0’
’0’
’0’
13
reserved
-
’0’
14
PLL Lock (Jasmine)
0 = unlocked, 1 = locked (read only)^{b ’0’}
15
Global HW Reset
0 = run mode, 1 = reset (write only)^{d ’0’}
[31:24] Chip Id
0 = Lavender, 1 = Jasmine (read only) -
a.RCLK is mapped on MODE[3] at Lavender.
b.Only applicable for Jasmine
c.Normally all register bits are read-write. As the PLL lock bit is status information only, no write
access is possible to it. The lock bit is for test operation only and should not be used.
d.Read access results always in a value of ’0’. Writing ’1’ starts global HW Reset function, writ-
ing ’0’ releases reset.
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