MB87P2020 Datasheet, PDF (89/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

SDRAM Controller
/* Build physical address from pixel address, function uses DRAM address */
/* window 0 only, pls ensure that DRAM mapping to MCU address is enabled */
dword phy_address (volatile byte layer, word x, word y) {
byte bpp;
/* Color depth lookup, 1/2/4/8/16/32
*/
byte ca;
/* DRAM Column Address (8 bit)
*/
word DomSzX; /* Layer Size X-Dimension (14 bit)
*/
dword XBits; /* Number of Bits for one Line (19 bit)
*/
word XRows; /* Number of Row blocks in X-Dimension (10 bit) */
word ra;
/* DRAM row address (without layer offset)
*/
byte ba;
/* DRAM bank address, Lavender only (2 bit)
*/
dword PhySDC; /* Physical address SDRAM Controller view
*/
dword PhyMCU; /* Physical address MCU view
*/
dword LayOffs; /* Layer Offset */
/* Determine Layer parameters and number of bits per line of pixels (x)*/
/* Formula: XBits = DomSzX << Shift = DomSzX * bpp
*/
bpp
= bpp_lookup(layer); /* layer color depth */
DomSzX = G0DSZ_X(layer);
/* layer pixel width */
LayOffs = G0PHA(layer);
/* layer start address */
XBits = DomSzX * bpp;
/* layer bitsize width */
/* Column address, Formula: CA = {Y[4:0], (X << Shift)[7:5]} */
/* Y: 32 lines, X: 8 words each block
*/
ca = ((y & 0x1f) << 3) + (((x*bpp)&0xff)/32);
switch (G0CLKPDR_ID) {
case 1: /* ----------- ID: Jasmine, GDC-DRAM, single bank ------------ */
/* Number of memory rows (grid of pixel blocks) in X-dimension
*/
/* each partially used row has to be considered (add 1 if remainder) */
/* Formula: XRows = XBits[18:8] + (XBits[7:0]? 1: 0)
*/
XRows = (XBits>>8) + ((XBits & 0xff)? 1: 0);
/* DRAM row address relative to layer start address, each row has a */
/* block size of 256 bit in X-dimension and 32 lines in Y-dimension */
/* Formula: RA = Y[13:5] * XRows + (X << Shift)[18:8]
*/
ra = y/32*XRows + (x*bpp/256);
/* combination of address bits: [19:10]ra, [9:2]ca, [1:0]byte
*/
PhySDC = LayOffs + (ra<<10) + (ca<<2);
break;
case 0: /* -------- ID: Lavender, GDC with external DRAM, 4 bank ----- */
/* Formula: XRows = XBits[18:9] + (XBits[8:0]? 1: 0)
*/
XRows = (XBits>>9) + ((XBits & 0x1ff)? 1: 0);
/* row block size is 512 bit in X-dim, 64 lines in Y-dim
*/
/* Formula: RA = Y[13:6] * XRows + (X << Shift)[18:9]
*/
ra = y/64*XRows + (x*bpp/512);
/* there exist 4 banks with same row address, thus each row block */
/* consits of 4 bannk parts
*/
/* Formula: BA = {Y[5], (X << Shift)[8]}
*/
ba = ((y>>5) & 0x1)*2 + (((x*bpp)>>8) & 0x1);
/* combination of address: [22:12]ra, [11:10]ba, [9:2]ca, [1:0]byte */
PhySDC = LayOffs + (ra<<12) + (ba<<10) + (ca<<2);
break;
default:
return -1; /* err: wrong chip ID */
}
/* add GDC0 offset (G0CMD is first GDC address) and ULB settings
*/
/* such as MCU Window 0 offset and subtract SDRAM offset
*/
/* check consistency if memory window is mapped and reachable
*/
if (!G0SDFLAG_EN)
return -2; /* err: SDRAM mapping not enabled */
if (PhySDC < G0WNDSD0 || PhySDC >= G0WNDSD0+G0WNDSZ0)
return -3; /* err: pixel address outside mapped Video RAM space */
/*
DRAM address
GDC base address
*/
PhyMCU = (dword) (char *) PhySDC + (dword) (char *) &G0CMD
/*
MCU offset
SDRAM offset
*/
+ (char *) G0WNDOF0 - (char *) G0WNDSD0;
return PhyMCU;
}
Figure 1-12: Logical to physical address conversion routine
Function Description
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