MB87P2020 Datasheet, PDF (193/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

Graphic Processing Unit
Mnemonic
(API-Names)
DIR_PixClkGate
PIXCLKGT_GT
PIXCLKGT_GON
PIXCLKGT_CP
PIXCLKGT_HC
DIR_CKlow
CKLOW_LLR
CKLOW_LLG
CKLOW_LLB
CKLOW_OP
DIR_CKup
CKUP_ULR
CKUP_ULG
CKUP_ULB
DIR_AClamp
ACLAMP_ACLR
ACLAMP_ACLG
ACLAMP_ACLB
DIR_DClamp
DCLAMP
DIR_MainEnable
MAINEN_DOE
MAINEN_HSOE
MAINEN_VSOE
MAINEN_VROE
MAINEN_CKOE
MAINEN_DACOE
MAINEN_REFOE
Table 4-1: GPU Register Set (continued).
Addr
Function
Initial
Value
3248 x Pixel clock gate control (by output of sync mixer 7)
[0] = gate type (0=AND, 1=OR)
0
[1] = gate enable (0=off)
0
[2] = clock polarity (0=true, 1=inverted)
0
[3] = divider (0=1:1, 1=1:2)
0
3250
Color key lower limits (according to physical color
space)
[23:16] = red channel
0
[15:8] = green channel
0
[7:0] = blue/monochrome channel
0
[24] = key out polarity (0=active high, 1=active
0
low)
3254
Color key upper limit (according to physical color
space)
[23:16] = red channel
0
[15:8] = green channel
0
[7:0] = blue/monochrome channel
0
Pin xo_ckey is activated, when all pixel channels
lie within (including limits) their respective limits
3258
Jasmine: Clamping value for analog outputs
Lavender: Clamping value for analog and digital
0
output
0
[23:16] = red channel
0
[15:8] = green channel
[7:0] = blue channel
325C
Clamping value for digital outputs (Jasmine only)
[23:0] = value output during blanking
0
3260
Main display output enable flags
[23:0] = digital data output enable
0
[24] = hsync output enable (when int. sync)
0
[25] = vsync output enable (when int. sync)
0
[26] = vref output enable (when int. sync)
0
[27] = ckey output enable
0
[28] = DACs output enable
0
[29] = reference voltage enable
0
SDRAM Controller Interaction
GPU_SDCPrio
3270
SDRAM Controller request priorities
SDCP_LP
[2:0] = low priority value (not used)
3
SDCP_HP
[6:4] = high priority value
7
SDCP_IFL
[15:8] = input FIFO load (read-only)
GPU Register Set
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