MB87P2020 Datasheet, PDF (47/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

Register Space
Jasmine default configuration
Register Space for GDC0
Register Space for other GDC
not configured
Configurable
SDRAM Space
Video Memory
User Logic Bus
Lavender default configuration
Register Space for GDC0
Register Space for other GDC
Video Memory window
0k
64k 0x00010000
256k 0x00040000
768k 0x000C0000
1M 0x00100000
not configured
Figure 1-3: Address space for Lavender and Jasmine with default configuration
2M 0x001FFFFF
Jasmine and Lavender support up to four devices for one chip select (ULB_CSX) signal. Also a mixed en-
vironment with different display controllers is possible. Register and SDRAM space are used by all con-
nected display controllers. Figure 1-4 shows a possible scenario for four display controllers which treats
only as an example. Many other configurations for SDRAM space are possible while register space is fixed
configured.
1.4.2 Register space
The size and location of configuration registers for every display controller is fixed. The size is set to
64 kByte for every display controller and the location is specified by Mode Pins (MODE[1:0]) as de-
scribed in Table 1-4.
Table 1-4: Address ranges for register space of different display controllers
Controller number
0
1
2
3
MODE[1:0]
00
01
10
11
Address range
00000h...0FFFFh
10000h...1FFFFh
20000h...2FFFFh
30000h...3FFFFh
Table 1-5 shows the register space for one display controller decoded by ULB address decoder. This decod-
er has a built in priority for the case of overlapping address areas. One display controller reserves the register
space for other controllers. Because the address decoder has a decoding priority it is not possible to overlay
the register space for other controllers with SDRAM windows.
Functional description
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