MB87P2020 Datasheet, PDF (284/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
Table 2-17: CCFL Driver Outputs, Output Characteristics
Parameter
Symbol
@20pF [ps]
@50pF [ps]
Jas
Lav
Jas
Lav
min. CCFL_FET2 Output Hold Time
t_OHCCFET2 3020 1830 3640 2450
max. CCFL_OFF Output Delay Time
t_ODCCOFF
8130
4730
10160 6760
min. CCFL_OFF Output Hold Time
t_OHCCOFF
2920
1730
3540
2350
max. CCFL_IGNIT Output Delay Time
t_ODCCIGNIT 8200 4740 10250 6770
min. CCFL_IGNIT Output Hold Time
t_OHCCIGNIT 2940
1710
3570
2330
a. For Jasmine related to internal MASTER_CLK, rising edge; for Lavender only the path delay was used.
2.5.10 Serial Peripheral Bus
For pulse shape and functional timing see SPB documentation. SPB timing regarding ULB_CLK is not of
interest. It is given for completeness only.
Table 2-18: SPB Pin Timing
Parameter
SPB_BUS Input Setup Time (falling)
SPB_BUS Input Hold Time
Symbol
t_SSPB
t_HSPB
Min [ps]
Jas
Lav
-1530 -3780
3100 4870
Max [ps]
Jas
Lav
-
-
Table 2-19: SPB Pin Timing, Output Characteristics
Parameter
max. SPB_BUS Output Delay Time
min. SPB_BUS Output Hold Time
Symbol
t_ODSPB
t_OHSPB
@20pF [ps]
Jas
Lav
11470 14890
2990 4670
@50pF [ps]
Jas
Lav
12500 14890
3010 5110
2.5.11 Special and Mode Pins
Mode[3:0], RDY_TRIEN, VPD, TEST are static configuration and test pins.
RESETX is asynchronous, thus no timing relation to any CLK can be specified. Maximum low pulse width
suppressed by spike filter is 5.5 ns. Only Jasmine has a spike filter implemented.
2.5.12 SDRAM Ports (Lavender)
See SDC documentation for description of external SDRAM interface timing configuration. Different from
measurement conditions above, SDRAM interface timing is evaluated from load capacitance connection of
C_L = 10pF for MIN conditions and C_L = 30pF for MAX conditions.
SDRAM clock output delay regarding internal core clock is shown in table 2-20. Other SDRAM interface
signals are specified regarding the SDC_CLK clock output pin. Same capacitive load is assumed for clock
and address/command/data pins. If different load capacitance is connected to the SDC_CLK pin than to the
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