MB87P2020 Datasheet, PDF (154/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
all layers, however, each layer may have its own offset for look-up. The Matrix is used for transforming
YUV (YCbCr) video data into RGB colorspace (cf. 3.7.2). It is supplemented with a gamma table (GamTbl)
to carry out a non-linear inverse gamma correction (cf. 3.7.3). The SpaceMap component merges the indi-
vidual layer color spaces to one common intermediate color space and further to one physical color space.
The Duty Ratio Modulator is used to provide pseudo gray levels (or colors) for displays with a low number
of bits per pixel. Color space conversion is explained more detailed in chapter 2.
1.2.4 LSA Function
The LSA (Line Segment Accumulator) is used to realize the vertical layer order in up to four planes. It acts
also as internal FIFO between GPU front end and back end, where clock domain transition between GDC
core clock and pixel clock takes place. Figure 1-4 shows the LSA structure.
The LSA contains two RAM blocks controlled by the BankManager component. These components per-
form the actual FIFO functionality. Three adjustment components (one for writing, two for reading) com-
plete the unit. They are used to efficiently employ the RAMs. There are two RAMs to allow for parallel
read-out when interfacing dual-scan displays.
Pixel data is fed in sequentially via WriteAdjust to one of the RAMs. Read-out is performed in parallel
through the respective ReadAdjust component. Z-ordering (vertical layer order) is achieved by writing pix-
els plane by plane sequentially into the LSA from bottom plane to topmost plane, thus overwriting pixels
hidden underneath others in higher planes.
from CCU
from DFU
Write
Adjust
Upper
LSA RAM
Lower
LSA RAM
Bank Manager
Read
Adjust
for Upper
to BSF
Read
Adjust
for Lower
Figure 1-4: LSA structure. Pixel data is prepared by WriteAdjust and then stored in one of the RAMs.
During read-out data is adjusted once again by the respective ReadAdjust.
1.2.5 BSF Function
The BSF (Bit Stream Formatter) unit performs the necessary preparations to actually output the picture on
a physical display (either with analog or digital interface). The BSF contains components for signal prepa-
ration and for synchronization. The structure is shown in figure 1-5.
The Timing component produces the synchronization frame for image data (see 3.9). It controls the LSA
read-out and provides positional information to the SyncSigs component. The XSync component supports
Timing when GDC is running with external synchronization. The SyncSigs component generates synchro-
nization signals for the physical display in a very flexible way (see 3.10). Further, it can produce a program-
mable interrupt. The components DigSwitch and DAC Sigs prepare pixel data for output on displays with
digital or analog interface, respectively. They select necessary signals and perform a delay compensation
between pixel and synchronization signals.
The ColorKey component allows the application of chroma-keying with GDC by detecting whether the pix-
el lie within a programmable color range (see 3.14.5).
Page 154