MB87P2020 Datasheet, PDF (180/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
Table 3-9: Function table for the Sync Mixer example.
Selected First-stage Signals
Desired Output
S4 = 0 S3 = 0 S2 = SPG1 S1 = SPG0 S0 = SyncSeq SMx = f(S0….S4)
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
1
0
1
0
0
0
1
1
0
0
0
0
1
1
1
0
Combinations [S4…S0] = 10000…11111 can never occur since S4 and need not be specified
S3 are selected constantly zero
It is recommended that S4…S0 are listed in order of binary number representation. This allows to take the
function result row immediately as register contents for the Sync Mixer function table, i.e. the last row is
interpreted as binary 32 bit number with the LSB in the first row and the MSB in the last. For the example
this would be [xxxx xxxx xxxx xxxx xxxx xxxx 0000 1000] binary, with x’s denoting arbitrarily set or reset
bits, since these will never be read out of the function table.
3.10.5 Sync Signal Delay Adjustment
Before the outputs of the eight Sync Mixers are connected to actual GDC pins, they are fed through a pro-
grammable delay stage. This allows the signals either to be left untouched or delayed for half a pixel clock
cycle. This delay can be set for each of the eight Sync Mixer output signals individually with the Sync
Switch register.
3.11 Pixel Clock Gating
The GPU allows to flexibly shape the pixel clock output at the respective pin. This is done with a program-
mable control register that defines how the output of Sync Mixer 7 affects the output pixel clock. Fig. 3-11
shows the resulting waveforms according to gate control settings. It should be mentioned that the control
by the mixer output is the only way to determine the position of clock edges when using the divided clock.
If the output clock is not gated, but divided, then the first rising clock edge occurs exactly at the same time
with the first rising edge of the pure internal pixel clock after reset.
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