MB87P2020 Datasheet, PDF (74/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
2.2 ULB initialization
ULB contains no lockable registers; so it is possible to write to every register at any time.
There is no initialization order for ULB but some general rules should be followed:
• For Lavender INTLVL register should normally be set to 0x00000000 in order to trigger interrupt on
high level (see section 1.6 for more details).
• SDRAM space for direct memory access has to be initialized and enabled for use. Write valid values to
WNDOFx, WNDSZx, WNDSDx and 0x00000001 to SDFLAG. Be careful about overlapping windows
when more than one GDC is connected to MB91xxxx (see section 1.4 for more details).
• Initialize IFUL or OFUL with valid limits before using FIFO limit flags (OFH,OFL,IFH,IFL) for in-
terrupt or polling. Otherwise default values will be taken as valid limits.
• Initialize MCU, IFDMA, OFDMA and DMAFLAG in this sequence with valid values in order to use DMA
for data transfer (see section 1.7 for details). Note that DMAFLAG_EN should be written at last because
it starts DMA transfer triggered by GDC.
• FLAGRES register should be initialized correctly before interrupt is enabled inside MCU or flags are
polled within user program in order to meet applications need.
• Read-only ULBDEB register exists only for debugging purpose; in normal applications flags in connec-
tion with FIFO limits should be preferred.
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