MB87P2020 Datasheet, PDF (41/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

1 Functional description
User Logic Bus
1.1 ULB functions
The “User Logic Bus Interface” (ULB) provides an interface to host MCU (MB91360 series). It is respon-
sible for data exchange between MCU and the graphic display controllers (GDC) Lavender or Jasmine¹.
The communication between MCU and the display controller is register based and all display controller reg-
isters are mapped in the MCU address space.
The task of ULB is to organise write- or read accesses to different display controller components, including
ULB itself, depending on a given address. For read accesses the ULB multiplexes data streams from other
components and has to control the amount of needed bus wait states using MCU’s ULB_RDY pin.
The ULB provides also a command- and data interface to so called ’execution devices’ (Pixel Processor
(PP) and Indirect Memory Access Unit (IPA)). These execution devices are responsible for drawing com-
mand execution or for the handling of SDRAM access commands. The data transfer to and from execution
devices is always FIFO buffered. In order to ensure a rapid data transfer between MCU and display control-
ler ULB contains one input and one output FIFO which are mapped to certain memory addresses within the
display controllers memory space. ULB controls the MCU port of these FIFOs (write for input FIFO and
read for output FIFO) while the ports to execution devices is controlled by the device itself.
The command interface has a two stage pipeline so command and register preparation is possible during
command execution of previous command. Most commands can have an infinite amount of processing data.
The FIFOs help to reduce the number of bus wait states.
Additionally to FIFO data exchange direct access to SDRAM and to initialisation registers is managed by
ULB. This direct SDRAM access maps the SDRAM physical into MCUs address space. Drawing functions
use a logical address mode for SDRAM access. Due to this direct (and also indirect via FIFOs) physical
access to SDRAM it can also be used to store user data and not only layer data (bitmaps, drawing results).
For direct SDRAM access (frame buffer or video RAM) the display controller internal SDRAM bus arbi-
tration influences the MCU command execution time directly via ULB bus wait states via ULB_RDY signal.
Therefore longer access times should be calculated for this kind of memory access. ULB is able to handle
memory or register access operations concurrently to normal command execution (FIFO based).
Beside normal data and command read and write operation ULB supports also DMA flow control for full
automatic (without CPU activity) data transfer from MCU to display controller or vice versa. Only one di-
rection at one time is supported because only one MCU-DMA channel is utilised. Also an interrupt control-
led data flow based on programmable FIFO flags is possible. In both cases the ULB bus is used for data
transfer.
ULB offers a set of some special registers controlling the display controller behaviour or show the state of
the controller with respect to MCU:
• Flag-Register
• Flag-Behaviour-Register
• Interrupt-Mask-Register
• Interrupt-Level-Register
• DMA-Control-Register
• Command Register
• SDRAM access settings
• Debug Registers
ULB also provides an interrupt controller that can be programmed very flexible. Every flag can cause an
interrupt (controllable by Interrupt-Mask-Register) and for Jasmine it is selectable whether the interrupt for
a certain flag is level or edge triggered. Furthermore for every flag the programmer can determine whether
the flag is allowed to be reset by hardware or not (static or dynamic flag behaviour).
1. The term ’display controller’ is used as generic name for Lavender and Jasmine and covers both devices.
Functional description
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