MB87P2020 Datasheet, PDF (179/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

Graphic Processing Unit
Const 0
SyncSeq
SPG0
SPG1
SPG2
SPG3
SPG4
SPG5
Mux
8 to 1
Ctrl
Reg
Mux
8 to 1
Ctrl
Reg
Mux
8 to 1
31
24
16
8
S0
S1
S2
Mux 32 to 1
S3
S4
0
FctTable
SyncMixer out
Ctrl
Reg
Mux
8 to 1
Ctrl
Reg
Mux
8 to 1
Ctrl
Reg
Figure 3-10: Basic structure of a Sync Mixer. Each of the five address lines of the 32 to 1 multiplexer
can be individually selected from any of the seven (plus one constant zero) first-stage signals. The out-
put is the result of a table look-up. The register FctTable contains the truth table of the Boolean
function calculated.
The concept of the sync mixers needs some explanation. In a first step the signals to be combined are se-
lected. These are referred to then as S0…S4 and form the address for the function table. This function table
is used to look up the result of the Boolean operation the five selected signals shall be subject to.
An example may help understand the topic. Assuming the outputs of three Sync Pulse Generators shall form
a combined signal with the function SMx = SyncSeq ∧ SPG0 ∧ SPG1 , one would proceed as follows.
At first, the Sync Mixer signals S0…S4 are assigned the Sync Pulse Generator outputs or constant zero by
programming the respective multiplexers. The next step is to build the function’s truth table, as shown in
table 3-9. Since the intended function has only three inputs, only eight entries need be specified.
GPU Control Information
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