MB87P2020 Datasheet, PDF (45/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

User Logic Bus
Mode
2 point mode
1 point mode
Table 1-2: Control signal sample modes for Jasmine
IFCTRL_SMODE[1:0]
10
11
Comment
sample point 1 and 2 (see figure 1-2)
have to have the same value
sample point 1 determines result value
Beside different sample modes Jasmine’s input synchronisation circuit contains priority logic to distinguish
between read or write access in the case that both control signals (ULB_RDX and ULB_WRX[n]) were de-
tected. Because the I/O controller (ULB read path) may detect a read access the ULB_RDX signal for read
access has the highest priority.
In Lavender a different input synchronisation circuit is implemented were always one sample point is used¹.
1.3.2 Read synchronization
For Lavender and Jasmine the ULB_RDY signal is gated by ULB_CSX. This means that the ULB_RDY sig-
nal goes immediately high after ULB_CSX=’1’ has been detected. It can not be ensured that correct data
are transferred to MCU in this case.
A protection against wrong tristate bus control signal switching is implemented in ULB. The bus driver is
only valid if ULB_CSX=’0’ and ULB_RDX=’0’. In all other cases ULB data bus is not driven.
Additionally to the described safety mechanisms which are implemented in both devices (Lavender and Jas-
mine) Jasmine has a programmable timeout for ULB_RDY signal generation. Therefore a counter is imple-
mented which is loaded with the value set in register RDYTO_RDYTO[7:0] at the beginning of a bus read
cycle². If the read value does not arrive within the counter runtime³ ULB_RDY signal is forced to ’1’ and
the MCU can finish the bus read cycle. Note that in this case data transferred to MCU are not valid. The
occurrence of a ULB_RDY timeout is reflected in the flag FLNOM_ERDY (ULB_RDY timeout error; see also
flag description in appendix) which has been implemented in Jasmine. Additionally to the error flag the ad-
dress where the timeout error occurred is stored in register RDYADDR_ADDR[20:0] in order to allow an
application running on MCU an error handling.
The ULB_RDY timeout counter can be disabled by turning RDYTO_RDTOEN off (set to ’0’).
In regular operation mode a ULB_RDY timeout can only occur if no memory bandwidth can be allocated by
the device handling the read request. Because the command execution is FIFO buffered (see also
chapter 1.1) and a read access from FIFO always returns a value within short time no timeout error can oc-
cur in normal command execution. Only a direct mapped memory read access (DPA read access; see also
chapter 1.4.3) in conjunction with very limited bandwidth may cause a ULB_RDY timeout error in normal
operation.
Beside this reason for timeout error in normal operation also disturbed bus transfers or bad signal integrity
may cause a timeout error.
1.3.3 DMA and interrupt signal synchronization
The DMA input and output signals (ULB_DREQ, ULB_DACK, ULB_DSTP) are used/generated in the
DMA Controller which is partly operating at ULB clock. Because these signals are generated in this part no
synchronisation is necessary. The signals influencing the DMA signal generation have to be synchronized
from Lavender/Jasmine core to ULB domain. For more details regarding DMA see chapter 1.7.
Another signal which needs to be transferred from Lavender/Jasmine core to ULB clock domain is the in-
terrupt request signal (ULB_INTRQ). In chapter 1.6 a detailed description of interrupt signal generation is
given. The synchronisation of the interrupt request signal is different between Lavender and Jasmine. Jas-
1. For Lavender sample point 1 is used to catch signals within ULB clock domain. Afterwards the caught sig-
nals will be sampled with core clock. As a result the real sample point depends on clock ration between ULB
and core clock.
2. A ULB bus read cycle is detected when ULB_CSX=0 and ULB_RDX=0.
3. The runtime ends when the counter reached value ’0’.
Functional description
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