MB87P2020 Datasheet, PDF (195/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

Graphic Processing Unit
In case of TV-conform timing being required two different pairs of ystart and ystop values are needed,
referred to as “odd” and “even”. They will be used alternating every other frame. Usually, the ystart val-
ues will be the same, whilst the ystop values differ by one. Thus it is possible to achieve an odd number
of lines for two consecutive frames.
Note: The complete entry of all necessary start and stop values is indispensable regardless of whether in-
ternal or external generation of sync signals is specified.
After determination of start and stop values sync signals can be specified as obtained from the display spec
if internal generation of sync signals is requested. For the majority of cases usage of sync pulse generators
as described in 3.10.2 should be sufficient. The basic task for their application is to determine the values for
start and duration of the required sync signals. These values are then converted to the “timing coordinates”
and entered into the appropriate GPU registers (addresses 0x3030 to 0x308C). For instance, a horizontal
sync signal that starts a display line and lasts for t_hsync would result in a value for its “switch-on” position
of p_{x, on} = xstart and a “switch-off” position of p_{x, off} = p_{x, on} + (t_hsync ⁄ t_ScanDot) , whilst the respective
y-components set to “don’t care”. Hence, this signal will provide a pulse of length t_hsync at the beginning
of each line. Position calculations are similar when the sync sequencer shall be used.
The required polarity and optional half cycle delay at the respective GDC pin is produced by the appropriate
sync mixer and sync switch settings as explained in 3.10.4 and 3.10.5.
External pixel clock
Depending on the specified GDC clock source for pixel clock (received from pin or derived from internal
clocks) the GPU can produce a tailored pixel clock signal at the clock pin for the display. Some displays
may require a gated clock that has periodical gaps. This behaviour is stated in the display spec. If necessary,
it can be produced using the clock gating described in 3.11 in conjunction with the settings for sync mixer
7 that controls this gate. The gate control signal is produced in the same manner as described above for the
sync signals.
Size, Timing, and Sync Dependencies
Although the values for physical display size, timing, and sync generation are programmable within wide
ranges, they are strictly interlocked for a certain display. Therefore, it is important to enter consistent values.
The previous paragraphs gave the rules to determine the values, here, table 4-2 shall conclude them as a
quick overview to check for correct magnitudes in correspondence to different scan modes for a display
with a given pixel resolution of X × Y (see also section 3.6).The timing values are approximative and have
to be tuned for blanking.
Table 4-2: Dependencies for size and timing according to scan mode for a display of given resolution.
Values
PX
PY
PXScanDots
SglScan
Scan Mode
DualScan
X
Y
-_BP----_iX--_t--_s-^×-_P----^Be---_r-ⁱ--_St--^s-_c--^P-_a---^e-_n--^r-_C--^P--_l--ⁱ-_o-^x--_c-^e--_k-^l
ZzagScan
basic horizontal (hsync)
cycle, i.e. xstop – xstart
≈ PXScanDots
≈ 2 × PXScanDots
basic vertical (vsync)
≈Y
cycle, i.e. ystop – ystart
≈ Y ⁄2
resulting frame period
≈ PXScanDots × Y
≈
P_-----X_----S_---c_---a_---n_----D_----o_----t_--s_----×_----Y_---
2
≈ PXScanDots × Y
GPU Register Set
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