MB87P2020 Datasheet, PDF (37/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

Clock Unit
Table 3-1: Mapping of clock sources, outputs and their enable bits
ClkPdR Control Bit
Clock Source
Clock Output
10
Master
Graphic Processing Unit
10
Pixel Clock^a
Graphic Processing Unit
a.Master and Pixel clock could be derived from one of four possible clock inputs (OSC_IN,
DIS_PIXCLK, ULB_CLK, RCLK/MODE[3]) with or without use of the PLL.
All clocks except VSC_CLKV can be used as Master or Pixel clock source. VSC_CLKV is for video inter-
face dedicated use only.
There are no special requirements for the quartz crystal parameters. At the case of overtone oscillation ad-
ditional external inductance L’=5-10uH and capacitor C’=10pF are needed. Two capacitors C=22pF have
to be connected from the OSC pins to ground in any case. Figure 3-2 shows recommendet circuit.
OSC_IN OSC_OUT
XQ
L’
C
C
C’
Figure 3-2: Crystal connection between pins OSC_IN and OSC_OUT
Without a crystal oscillator connected (e.g. extrnal oscillator) the clock has to fed in the OSC_IN pin.
3.2 Clock Unit Programming Sequence
This section gives a recommendation for the sequence for GDC clock configuration. In general the Clock
Unit registers should be configured before all other GDC setup information.
• Apply stable clock and do a hardware reset.
• Write ClkConR for the required mode. Clock gates are disabled per reset default.
• Switch on PLL and optionally apply software reset (Set bits [11] and [15] in ClkPdR).
• Clear software reset bit (Optional, only if set before).
• Wait until APLL has stabilized and locked (lock-up time)¹
Polling of lock bit is optional and not sufficient that PLL locking process has finished. This signal is
for Fujitsu test purpose only. APLL lock-up state is reached if Lock bit becomes stable ’1’. This is
guaranteed after specified PLL lock-up time of 500us.
• Set required clock enable bits to open the clock gates.
1.The lock up time measured from PLL start (CLKPDR_RUN=’1’) to lock state
(CLKPDR_LCK=fixed ’1’).
Clock Setup and Configuration
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