MB87P2020 Datasheet, PDF (92/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
2 SDRAM Ports
From timing point of view critical is specially read accesses due to the fact, that delays of clock to the mem-
ory device and data back from memory to GDC have to be summarized relative to the internal rising clock
edge. Figure 2-3 shows when read data from SDRAM are valid after feeding back to GDC. There is the
additional restriction for keeping the setup and hold times of the data input registers, which reduces the valid
region of sampling time additionally. That’s why active clock edge of the input flip-flop has to be inside the
gray marked region. Best decision is the mid of this to have enough space for deviations. There are different
possibilities to compensate the part of total delay which is larger than one clock period. One is to insert a
delay buffer in the clock lines of the input registers, another is to sample data on falling clock edge of input
register. Additional to the input register clock delay there are to satisfy the hold time requirements of all
SDRAM input signals (outputs from GDC). Due to the fact that the input signal timing has to be relative to
the receiving clock at the SDRAM, this depends much on the delay of output clock buffer and clock wire
delay.
Core:
CLK
SDRAM:
CLK
SDRAM:
D
Core:
D
tdCLK
tAC
tOH
tdD
tdD
tsD
thD
Figure 2-1: SDRAM Interface Timing
Sampling area
2.1 External SDRAM I-/O-Pads with configurable sampling
Time (Lavender)
Additional to the tri state control there is an special timing feature implemented at the SDRAM ports. Inside
the SDC there is a configurable hold time adjustment for the outputs and sampling time adjustment for the
data input.
The implemented solution uses configurable delays for each signal group (addresses and control signals, tri
state control, write data and read data). In this way it’s possible to compensate the influence of the board
layout in a comfortable way.
Registers for the SDRAM interface control the timing of the ports. Four different timings have to be satis-
fied:
• Hold time for SDRAM input pins address, command and DQM (tDCBTaout)
• Hold time for SDRAM data input pins (tDCBTdout)
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