MB87P2020 Datasheet, PDF (333/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

1 Special hints
Hints and Restrictions
1.1 IPA resistance against wrong settings
Invalid settings for minimum transfer block sizes lead to IPA deadlock from which it can only recover by
reset. At minimum a value of 1 has to be given for the output FIFO (block size of zero makes no sense) and
a minimum value of 2 for the input FIFO should be setup. Input FIFO needs at least one address/data pair
for IPA.
Table 1-1 gives an overview and a classification about the described problem.
Table 1-1: Overview for IPA resistance
Subject
Description
Classification
Effects without
workaround
Solution/Workaround
Concerned devices
Testcase
Description
Smaller block sizes does not make sense since a block should contain at
least one word.
Input FIFO contains address and at least one data word.
Output FIFO contains at least one data word.
Hint
The system may hang with wrong settings.
Do not use forbidden settings.
Escape only with HW-Reset.
No workaround required.
MB87J2120 (Lavender)
MB87P2020 (Jasmine)
fixed for MB87P2020-A (Jasmine redesign)
EMDC: IPA.1 and SDC.3
(Limits can be set in ’mkctrl’.)
1.2 ULB_DREQ pin timing to host MCU
ULB_DREQ reaction time is critical if only one wait state for User Logic Bus (ULB) cycle is set up. Writing
per DMA ‘demand mode’ can lead to additional transferred data after ULB_DREQ tied low. Jasmine can
handle this additional data by an two words deep overflow buffer. Thus no data will be lost.
For Lavender the count of waitstates can be set equal or greater than two.
Writing to input FIFO in DMA block/step/burst mode and reading from output FIFO with DMA (both
block/step/burst and demand mode) transfers correct amount of data in any case for Jasmine and Lavender.
A detailed description about this topic can be found in hardware manual (chapter B-2.1.7) and in a DMA
application note.
Table 1-2 gives an overview and a classification about the described problem.
Table 1-2: Overview for ULB_DREQ timing
Subject
Description
Classification
Description
Reaction time for ULB_DREQ pin for write accesses is critical if one wait-
state is set up.
Hint
Special hints
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