MB87P2020 Datasheet, PDF (204/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
6 Functional Peculiarities
6.1 Configuration Constraints
Due to the great flexibility provided by the extensive programmability there is no built-in precaution
against illegal, not supported or absurd register settings. Programming has to be carried out with a thor-
ough understanding of the features explained in this document. Items to pay attention to include (but are not
limited to):
• Window size does not exceed domain size in every dimension
• Window size greater than zero
• First pixel lies within window size
• Offset within physical display dimensions
• CLUT offset may cause wrap-around for look-up
• Color space settings confirming to tables 2-1 and 2-2, chapter 2
• Non-transparent layers covering others
• Layers multiply exposed (i.e. identical settings for Z-order register entries, this is a waste of memory
and processing bandwidth)
• Disabled background will lead to garbage pixels in areas not covered by non-transparent layer con-
tents
• Values for master timing X stop must be greater than or equal to PXScanDots, master timing Y
stop values must be greater than or equal to PhysSizeY, otherwise internal FSMs will hang
• Sync pulse generator and sync sequencer entries should lie within timing range determined by the
master timing registers
• Combination of physical color space and bit stream format confirming to table 3-4, chapter 3
• All necessary output pins enabled for connected physical display
• Color key limits according to physical color space
• Register set entries that influence bit stream timing (master timing values, physical color space code,
bit stream format code, display dimensions etc.) are locked with MasterTimingOn to prevent
internal FSMs from hanging. These values may only be set or changed when MasterTimingOn is
reset. These registers are marked in table 4-1.
6.2 Bandwidth
• Bandwidth is an important issue when it comes to usage at performance limits. Unfortunately, it is
hard to estimate in advance whether certain settings will cause constraint violations, since other
GDC-units, the GPU shares the VideoRAM with, have an influence hard to predict. The rules given
in chapter 5 should help checking for possible bottlenecks.
As a support for software development GPU can trigger an interrupt when it suffers from critical data
shortage. The interrupt is actually raised when the LSA runs empty (an empty DFU input FIFO does
not constitute a data shortage as such, since this state can only be temporary and recoverable). In the
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