MB87P2020 Datasheet, PDF (69/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

User Logic Bus
The chosen DMA mode is demand mode which should be set inside MCU and display controller. Addi-
tionally for display controller the output FIFO is selected for DMA operation and signal inversion and
tristate behaviour is not selected according to board implementation (see chapter 1.3.4). The DMA trigger
limit for output FIFO is set to 1 (register: G0OFDMA) which means that every new data word in output FIFO
causes a DMA transfer. In demand mode this ensures an empty FIFO after DMA operation but this causes
also a lot of protocol overhead because a handshake between display controller and MCU is necessary for
every data word. Therefore transfer performance may decrease slightly.
The loop labelled with ’waitdma2’ at the end of figure 1-18 stops program execution until the end of DMA
transfer. The following code can assume that data are transferred from display controller to MCU also as
result of this low FIFO limit.
Figure 1-19 shows an example where a RLE compressed bitmap is transferred to display controller with
help of DMA. This example uses C-API functions which are described in detail in a separate manual. See
C-Comments for a short explanation.
/*****************************************************************************/
/* Constant declarations */
/*****************************************************************************/
// Picture infos:
// - RLE compressed.
// - 16BPP.
// - 111 x 43 pixel, origin: 0, 0
// Picture dimensions
const hd_fujitsu_x = 111;
const hd_fujitsu_y = 43;
// Number of data words for ’hd_fujitsu’ array
const hd_fujitsu_num = 800;
// Array definition
const dword hd_fujitsu_array[] = {
0xeeffdfb8,
0xffdf04fd,
// ..data..
0xdf000000};
void main(void)
{
// use DMA (demand mode)
// ---------------------------------------------
// Set up MCU- and GDC-DMAC
// ---------------------------------------------
// ULB_DMA_HDG(dummy,dummy,mode,block,direction)
// mode: 00: block/step, 01: burst, 10: demand
// block: block size (1 in demand mode)
// direction: 1: input FIFO; 0: output FIFO
ULB_DMA_HDG(0, 0, 2, 1, 1);
// ---------------------------------------------
// write parameter and command (see API description)
// ---------------------------------------------
GDC_CMD_PtCP(0x0,hd_fujitsu_x-1,0x0,hd_fujitsu_y-1,0x0,0x0,0x0,0x0,0);
// ---------------------------------------------
// activate DMA transfer
// ---------------------------------------------
GDC_FIFO_INP((dword *)hd_fujitsu_array, (word)hd_fujitsu_num, 1);
// ---------------------------------------------
// wait for end of transfer
// ---------------------------------------------
while ((DMACA0 & 0x80000000) != 0);
// ---------------------------------------------
// send NoOp in order to flush input FIFO
// ---------------------------------------------
Functional description
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