MB87P2020 Datasheet, PDF (20/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
Table 2-1: Lavender and Jasmine features in comparison
MB87J2120 (Lavender)
MB87P2020-A (Jasmine)
• On-Chip Video DAC, 50M Samples/s (dot clock)
• Flexible three-stage sync signal programming (trigger position/sequence, combining and delay) for
up to 8 signal outputs
• Colour keying between two limits
• Brightness modulation for displays with a Cold Cathode Fluorescence Lamp back-light
• Display resolution/drawing planes up to 16383 pixels for each dimension
• 4 layer + background colour simultaneous display and graphic overlay, programmable Z-order
• Blinking, transparency and background attributes
• Free programmable display section of a layer
• Separable Colour LUT with
256 entries x 24 Bit
• Colour LUT expansion to 512 entries
• Duty Ratio Modulation (DRM) for pseudo hue/grey levels
• Hardware support for 16 layers, usable for graphic/video without restrictions
• Performance sharing with adjustable priorities and configurable block sizes for memory transfers en-
able maximal throughput for a wide range of applications
• Variable and display independent colour space
concept: Layers with 1, 2, 4, 8, 16, 24 bit per
pixel can be mixed and converted to one dis-
play specific format (logical-intermediate-
physical format mapping)
• Additional GPU a YUV to RGB converter in
order to allow YUV coded layers
• Additional Gamma correction RAMs are in-
cluded (3x256x8Bit)
Physical SDRAM access
• Memory mapped direct physical access for storage of non-graphics data or direct image access
• Indirect physical memory access for high bandwidth multipurpose data/video memory access
MCU interface
• 32/16 Bit MCU interface, designed for direct connection of MB91xxxx family (8/16/32Bit access)
• DMA support (all MB91xxxx modes)
• Interrupt support
Video interface
• Video interface VPX32xx series by Micronas • Additional CCIR conform input mode
Intermetall, Phillips SAA711x and others
• Video synchronization with up to 3 frame buffers
Clock generation
• Flexible clocking concept with on-chip PLL and up to 4 external clock sources:
- XTAL
- ULB bus clock
- Pixel clock
- Additional external clock pin (MODE[3]/RCLK)
• Separate power saving for each sub-module
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