MB87P2020 Datasheet, PDF (315/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

Register Description
Table 1-2: Register address space for Jasmine and Lavender
Register
Bits Group
Name Address
Name
Description
Default
value
CLKCR
0xFC00
31:30 DCS
oo
29:24 SCP
23:22 PCS
oo
oo
21:16 PFD
15 SCSL
oo
oo
14 PCSL
oo
13 IPC
oo
12 PCOD
oo
11 DBG
o
10:0 PCP
oo
Clock configuration register
Direct clock source
00: Crystal (pins OSC_IN
and OSC_OUT),
01: Pixel clock (pin
DIS_PXCLK)
10: MCU clock (pin
ULB_CLK)
11: Reserved clock (pin
RCLK)
System clock (CLKK) pres-
caler
PLL clock source
00: Crystal (pins OSC_IN
and OSC_OUT),
01: Pixel clock (pin
DIS_PXCLK)
10: MCU clock (pin
ULB_CLK)
11: Reserved clock (pin
RCLK)
PLL feedback divider
System clock (CLKK) select
0: direct clock source
1: PLL clock source
Pixel clock (CLKD) select
0: direct clock source
1: PLL clock source
Pixel clock (CLKD) invert
0: not inverted
1: inverted
Pixel clock output
(DIS_PXCLK) disable
0: internal pixel clock (CLKD
output)
1: external pixel clock
(DIS_PXCLK input)
1: Core clock (CLKK) debug
mode (output at pin
SPB_TST)
Pixel clock prescaler value
00
0
00
0x00
0
0
0
1
0
0x000
Register Description
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