MB87P2020 Datasheet, PDF (58/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
once (e.g. per DMA or interrupt controlled) it may be easier to read data from FIFO as soon as they appear.
Figure 1-10 shows a code example where this is demonstrated.
// data array
dword data[SIZE];
// loop over package size
for (k=0; k < SIZE;k++){
// wait as long as OFIFO is empty
// make sure G0FLNOM_OFE is to dynamic!!!
while (G0FLNOM_OFE);
// read data into array
data[k] = G0OFIFO;
}
Figure 1-10: C-example for reading data continuously
1.5.3 Structure of command controller
The ULB contains a command controller which is responsible for controlling so called ’execution devices
(ED)’ within display controller. These EDs are responsible for command execution and data processing.
In current implementation of Lavender and Jasmine four execution devices are handled by ULB command
Table 1-11: Execution devices within Lavender and Jasmine
Execution device
Pixel Engine (PE)
Pixel Processor
(PP)
Physical memory
access unit (DIPA)
Memory Access
Unit (MAU)
Memory Copy
(MCP)
IPA
Function
• Drawing of graphical primitives
• Drawing and RLE decompression of bitmaps
• Writing and reading of pixel-addressed data
• Copying of pixel-addressed blocks within SDRAM
memory
• Writing and reading of word-addressed data via
input- and output FIFO
controller. An overview on execution devices and their functions is given in table 1-11. See specifications
of these devices for a detailed description.
Most of display controller commands are so called ’infinite commands’ which means that these commands
have an unlimited number of processing data. The stop condition for infinite commands is writing a new
command. Therefore a second register is needed which contains the currently executed command. This reg-
ister is controlled by hardware and not writeable by MCU. Jasmine has the possibility to watch currently
executed command with a read only debug register (CMDDEB; see chapter 1.5.5 for details).
Between the two command registers the Command Decoder is located. The command write time from com-
mand to shadow command register is determined by hardware because it depends on the execution state of
previous command. The structure of Command execution unit within ULB is shown in figure 1-11.
In order to avoid command pipeline overflow and to implement a command flow control between display
controller and MCU a flag ’command write enable’ (FLNOM_CWEN) is implemented. This flag signals that
a new command can be written into command register (FLNOM_CWEN=1). By writing the new command
the old command is still executed and the pipeline is filled with two commands which can be watched from
MCU by ’CMD_WR_EN=0’¹.
1. This is only true when this flag is set to dynamic behaviour which is the reset value. See section 1.6 for a
detailed explanation.
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