MB87P2020 Datasheet, PDF (152/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
1.2 GPU Overview
1.2.1 Top Level Structure
VideoRAM
SDC
DFU
Data
Fetching
Unit
Ctrl Bus
CBP
Control Bus Port
CCU
Color
Conversion
Unit
LSA
Line
Segment
Accu
BSF
Bit
Stream
Formatter
I / O Buffer
DAC
Display
Figure 1-1: GPU top level structure. Thick black lines show the flow of pixel data, thin black lines the
control flow. Thick gray lines represent register set data.
Figure 1-1 shows the GPU top level structure, which consists of the four main components DFU, CCU,
LSA, and BSF. The CBP is actually only an auxiliary unit to couple the other units to the system-wide con-
trol bus. Control registers are assigned their respective units, so there is no GPU-global register set (al-
though it appears as such for the programmer). The functions of each unit will be discussed briefly in the
following sections.
1.2.2 DFU Function
The DFU (Data Fetching Unit) interacts with the SDC (SDRAM Controller) to transport pixel data from
VideoRAM into the GPU pipeline. Since VideoRAM is a shared resource within GDC, the DFU is equipped
with 4KBits of FIFO to balance data rate and optimize RAM usage by enabling burst accesses.
DFU structure is shown in figure 1-2. Pixels from layers displayed simultaneously are fetched sequentially
according to their respective start points, display offsets, color resolutions, and vertical stacking. This is car-
ried out by the Fetch FSM. The data obtained from SDC is put into the FIFO, from where it is read out later
by the PixelPump and fed through the CCU into the LSA, where the vertical (Z-)order is actually real-
ized.The PixelPunp is also used to carry out the chrominance demultiplexing for YUV422 layers (cf. 3.7.1).
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