MB87P2020 Datasheet, PDF (48/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
CSX
MODE[1:0]
GDC 0: gdc_offset0
GDC 0: gdc_size0
GDC 3: gdc_offset1
GDC 3: gdc_size1
GDC 0: gdc_offset1
GDC 0: gdc_size1
GDC 1: gdc_offset0
GDC 1: gdc_size0
GDC 1: gdc_offset1
GDC 1: gdc_size1
GDC 0 (64k)
64k
GDC 1 (64k)
128k
GDC 2 (64k)
192k
GDC 3 (64k)
000111_{0 0 0 0 0 1 1 1 1 1 0000000000111111111100001111}000111_{0 0 0 0 0 1 1 1 1 1 0000000000111111111100001111}000111_{0 0 0 0 0 1 1 1 1 1 0000000000111111111100001111}000111_{0 0 0 0 0 1 1 1 1 1 0000000000111111111100001111}000111_{0 0 0 0 0 1 1 1 1 1 0000000000111111111100001111}000111_{0 0 0 0 0 1 1 1 1 1 0000000000111111111100001111}000111_{0 0 0 0 0 1 1 1 1 1 0000000000111111111100001111}01_{0 0 1 1 001101}⁰⁰¹¹_{0 0 0 1 1 1 0000000011111111000111}^256k
0 ^{0 0 0 0 0 0 0 0 0 0 0 0} 1 ^{1 1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0 0 0 0 0} 1 ^{1 1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0 0 0 0 0} 1 ^{1 1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0 0 0 0 0} 1 ^{1 1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0 0 0 0 0} 1 ^{1 1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0 0 0 0 0} 1 ^{1 1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0 0 0 0 0} 1 ^{1 1 1 1 1 1 1 1 1 1 1 10 0} 1 ^{1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 2 21}
Register space
SDRAM space
empty space
010101010101
SDRAM
000111001101^{G001101DC0011010 001101001101}
0 ^{0 0 0} 1 ^{1 1 10 0 1 1} 0 ⁰ 1 ^{10 0 1 1} 0 ⁰ 1 ^{10 0 1 1} 0 ⁰ 1 ^{10 0 1 1} 0 ⁰ 1 ^{10 0 1 1} 0 ⁰ 1 ¹
SDRAM
0101^G01^DC01¹ 0101
GDC 0: sdram_offset0
GDC 0: gdc_size0
GDC 0: sdram_offset1
GDC 0: gdc_size1
GDC 1: sdram_offset1
GDC 1: gdc_size1
GDC 1: sdram_offset0
GDC 1: gdc_size0
SDRAM
GDC 2
0 ⁰ 1 ^{10 0} 1 ^{10 0} 1 ^{10 0} 1 ^{10 0} 1 ^{10 0} 1 ¹
SDRAM
GDC 3
GDC 3: sdram_offset1
GDC 3: gdc_size1
Figure 1-4: Address space example for four graphic display controller (GDC) devices
Within the upper part of register space (address range 0xFC00-0xFFFF) for one display controller a re-
served area is located. This area is needed for internal and/or external devices with the same ULB_CSX sig-
nal as the display controller which have their own address decoders. Internal devices using this area are
currently the Clock Unit (CU) and the Serial Peripheral Bus driver (SPB) (see also table 1-5).
Note that Lavender register space is compatible to Jasmine register space. Only new registers for new func-
tions were added or not needed registers were removed but the same function can be found on the same reg-
isters. There are only a few exceptions (see register list for more details).
Table 1-5: Register address space for GDC
Priority
1
Address range
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
ULB addressed Target component/Register
component
Command register
Input FIFO
Output FIFO
Flag register (normal access)^a
ULB
Flag register (reset access)^a
Flag register (set access)^a
Interrupt mask (normal access)^a
Interrupt mask (reset access)^a
0x0020
Interrupt mask (set access)^a
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